Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: A processing apparatus has a master processing module and a plurality of slave processing modules. The master processing module has a master recording unit and a slave recording unit recording part of the data recorded in the master recording unit. The slave processing modules access the master processing module when it is necessary to access the data recorded in the master recording unit. When the data to be accessed from one slave processing module is recorded in the slave recording unit, the master processing module transmits the data to be accessed, from the slave recording unit to the one slave processing module. In the processing apparatus such as a base transceiver station communicating with transceivers such as mobile telephones, a reduction in the overall cost of the apparatus and an efficient internal communication are realized, and the overall processing time is reduced.

Abstract: Handling interrupts within an information handling system including entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the received interrupt in accordance with an ordered list of a plurality of possible interrupt sources, dispatching an appropriate interrupt handler to resolve the identified at least one source of the received interrupt, noting a frequency of occurrence of each indentified at least one source generating a received interrupt over time, and recording the ordered list of possible interrupt sources in response to the noted frequency, wherein the possible interrupt sources with higher frequencies are placed in the beginning of the ordered list.

Abstract: Very small non-volatile memory cards are modified to include a connector to which a connector on a separate data input-output card electrically and mechanically mates when pushed together. The input-output card transfers data directly between an external device and the non-volatile memory, without having to go through the host to which the memory card is connected. The input-output card communicates with the external device through a wired or a wireless communication channel.

Abstract: A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value. The initiator writes the value of the target-specific counter into the tag field of the packet header, and also writes an identifier of the initiator into the header. Then the initiator sends the packet to the target on the PCIe data bus. Upon receipt of the packet, the target reads the identifier and checks the value against the appropriate initiator-specific counter on the target. When the value is not equal to the initiator-specific counter on the target, then it generates an error message. An additional memory write with specific data is posted from the initiator to the target. A memory read is posted of the additional memory write location from the initiator to the target.

Abstract: Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided.

Abstract: Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.

Abstract: A control system includes a host device and a string of slave devices coupled in series. The host device includes a first transmission unit operable to transmit an encoded control signal provided by a first processing module, and to receive an encoded feedback signal for subsequent decoding by the first processing module. Each of the slave devices includes: a driven member responsive to a driving signal for generating an event; a driving unit operable to provide the driving signal; a detection unit generating an initial feedback signal based on the event; a second processing module capable of decoding the encoded control signal so as to drive the driving unit when an address code in the encoded control signal corresponds to the slave device, and of generating the encoded feedback signal; and a second transmission unit operable to receive the encoded control signal, and to transmit the encoded feedback signal.

Abstract: Certain embodiments of the invention may include receiving at least one message via a single bus interface to which each integrated Ethernet controller may be coupled. A bus identifier, bus device identifier and bus function identifier corresponding to the received message and which identifies a particular one of the integrated Ethernet controllers may be determined. The received message may be transferred to the particular integrated Ethernet controller based on the determined bus identifier, bus device identifier and bus function identifier, which were previously generated. The method may further include associating a bus function with the particular integrated Ethernet controller and mapping the associated bus function identifier to the bus function. A bus function process may be associated with the particular integrated Ethernet controller. The bus identifier may be associated with the single bus interface and the device identifier may be associated with the plurality of integrated Ethernet controllers.

Abstract: An address assignment mechanism. A computer system may include one or more types of slave devices. Each slave device includes an internal device ID. Slave devices of the same type include the same internal device ID. The master device may broadcast a message through the use of a protocol to each of the slave devices to initiate an address assignment operation. Each of the slave devices determines whether the broadcast device ID included in the broadcast message matches the internal device ID associated with the slave device. If the broadcast device ID matches the internal device ID, the linear bus address included in the broadcast message is assigned to the slave device. The bit size of the linear bus address may be smaller than that of the broadcast device ID. After the address assignment operation, the master device may communicate with the slave device using the assigned linear bus address rather than the device ID.

Abstract: A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In one embodiment, an exemplary silo routing circuit is formed upon a semiconductor substrate and routes data among a number of reconfigurable computational elements. The silo routing circuit comprises a plurality of input terminals and a plurality of output terminals. Further, the silo routing circuit includes a multi-stage interconnection network (“MIN”) of switches configurable to form data paths from any input terminal to any output terminal.

Abstract: A device including a storage component to store a driver for the device, and a device protocol handler to enable automatic upload of the driver to a storage subsystem of a processor based system in response to the device being communicatively coupled to a bus of the processor based system.

Abstract: A multimedia interface device for the transfer of information in a communications network comprises: at least two connection means to which, respectively, at least two sending devices can get connected by means respectively of two communications links compliant respectively with two protocols; means of connection to a single remote switching device by means of a single cable, the switching device comprising at least switching means between at least two ports; means to mix the information sent out by sending devices into only one stream of information in the form of segments being able to contain part of the information; and means to transfer the stream of information in the form of segments on at least one pair of cable to the switching device to which it is connected according to a third protocol.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.

Abstract: In one embodiment, the present invention includes a bus controller including a mutual exclusion unit to receive a data transmission request from first and second agents and to select one of the agents for servicing based on which agent is the first to send the request, multiple selection units controlled by the mutual exclusion unit, and a two-phase register coupled to at least one of the selection units to transmit data from the selected agent. Other embodiments are described and claimed.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Abstract: Systems and methods for enabling arbitrary components to transfer current, contextual data between each other without requiring prior knowledge of each other. The contextual data may include executable computer language instructions or a type, operating status, identity, location, administrative domain or environment information of the components or its users. The system includes a set of arbitrary components associated with one or more universal interfaces. The one or more universal interfaces may include mobile code, a contextual interface, a notification interface, a user interface and a data source interface. A first component at least has a universal contextual interface. A second component may invoke the universal contextual interface and execute associated instructions to transfer contextual data between the first component and the second component.

Abstract: A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each of the interrupt pins is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with the least interrupt checking number.