Abstract: A method and computer system for dynamically selecting an optimal synchronization mechanism for a data structure in a multiprocessor environment. The method determines a quantity of read-side and write-side acquisitions, and evaluates the data to determine an optimal mode for efficiently operating the computer system while maintaining reduced overhead. The method incorporates data received from the individual units within a central processing system, the quantity of write-side acquisitions in the system, and data which has been subject to secondary measures, such as formatives of digital filters. The data subject to secondary measures includes, but is not limited to, a quantity of read-side acquisitions, a quantity of write-side acquisitions, and a quantity of read-hold durations. Based upon the individual unit data and the system-wide data, including the secondary measures, the operating system may select the most efficient synchronization mechanism from among the mechanisms available.

Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.

Abstract: A method for address filtering is described. A host interface including device registers is provided. A user program is initiated for loading of data and control information respectively into a first data register and a control register of the device registers. Responsive to the loading, hardware is initiated for writing of information loaded into the first data register into a host interface register, where the first data register is associated with an address table configuration entry and the information includes read or write information and address information. Responsive to the read or write information and the address information, a multicast address is obtained from storage; a first portion of the multicast address is deposited into the first data register; and a second portion of the multicast address is deposited into a second data register.

Abstract: A system for parallel data transmission including a master device and a slave device is provided. The master device includes a first and a second I/O ports for outputting a read signal and a write signal, respectively. The slave device includes a third and a fourth I/O ports electrically coupled to the first and the second I/O ports, respectively. When the master device outputs the read or the write signal, the slave device transmits status information of the slave device to the master device after the master device has transmitted an address latch enable signal and before the slave device receives the address latch enable signal which is active. The master device outputs an address signal after transmitting the address latch enable signal and latches the address signal for the addressing for reading or writing data after the slave device has received the address latch enable signal.

Abstract: A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries. A queuing circuit having a plurality of registers interconnected by 2:1 multiplexers is also provided. The circuit is arranged such that each register receives either its own current contents or the contents of a higher order register during each register write cycle.

Abstract: Method and apparatus for address filtering for a media access controller is described. An application specific integrated circuit block located in a programmable logic device includes a media access controller. The media access controller includes an address filter, which includes: address filter modules, a first logic tree coupled to each of the address filter modules and configured to provide a frame drop signal for delineation between a dropped frame and an address filtered frame; and a second logic tree coupled to each of the address filter modules to provide an address valid signal.

Abstract: Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a stop condition on the I2C bus, operating a timing circuit (40) to count a predetermined delay from the stop condition, and operating the control circuit (87) in response to the start bit to automatically send a start condition on I2C bus after the delay has elapsed. The control circuit (87) automatically sends the address byte on the I2C bus after the start condition has been sent.

Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Abstract: A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is determined by a component such as a processor. If the bus clock frequency is at a first, relatively high frequency, data is driven onto the bus in an earlier time window (e.g., near the rising edge of the bus clock signal). If the bus clock frequency is at a second, lower frequency, data is driven onto the bus in a second, later time window (e.g., near the center of the high level of the bus clock). Accordingly, the time window for receiving the data driven onto the bus need not be changed (e.g., near the rising edge of the next bus clock signal) allowing components to work effectively with both bus clock frequencies.

Abstract: A method of using a bus, includes: determining whether a subject unit among a plurality of units corresponding to masters obtaining a bus use permission from an arbiter uses the bus as a master to transfer data to/from a first unit corresponding to a slave; and converting the first unit into a master when the subject unit does not use the bus in order to allow the first unit to use the bus as a master, when the subject unit is determined not to be using the bus.

Abstract: Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a first function signal are asserted, the corresponding second signals of are asserted in response and a function is performed on the boards. But, if any of the second signals are asserted, none of the first signals is asserted in response. Test signals on boards are thereby isolated from test signals coupled to all the boards on the system, so a fault on any signal in any second set of signals will not propagate to the first set of signals.

Abstract: A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.

Abstract: The invention relates to a network subscriber station and to a method for operating a network subscriber station for a network of distributed stations, particularly a network of IEEE 1394 network subscriber stations, which are connected by means of a data bus. The network subscriber station comprises at least three memory areas for operation-dependent interface configuration data and pointer means, which comprise electronic pointers to the at least three memory areas, and driver means for handling electronic data in the at least three memory areas and for electronic data transfer between the at least three memory areas.

Abstract: A bi-directional serial interface for serial communication having a control line to facilitate the transmission of data to and from a microcontroller and a serial interface module. The control line can be used by both the microcontroller and the serial interface module to send controlling signals such as start signals, receipt acknowledge signals, error signals, and stop signals. By having a dedicated control line that can be used by both the sending device and the receiving device, the present invention allows the initiation of a communication session by either the microcontroller or the serial interface.

Abstract: An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are present on the bus, the initiator provides a write or a read request signal that is activated and deactivated synchronously. The initiator then receives from the target unit a grant signal that is activated and deactivated synchronously. After the grant signal is deactivated, for a write operation, the initiator provides a number of write data items on the bus synchronously for capture by the target unit. For a read operation, the target provides a number of read data items on the bus synchronously for capture by the initiator unit. One data item provided in each clock cycle of the clock signal and the number of data items is determined by the length information provided.

Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.

Abstract: Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Abstract: A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during which interrupts will be measured for a processor. The amounts of time spent by the processor during the interrupt processing period in interrupt context can be measured. Another operation is detecting an interrupt storm occurring for the processor based on the amounts of time spent by the processor in interrupt context. The interrupts received by the processor can then be restricted for a period of the processor's total processing time when an interrupt storm has been detected.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU contained LSI includes a CPUa, common address/data buses 111 and 112 connected to the CPUa, CPUb address/data buses 211 and 212 connected to a CPUb, and a bus adjusting circuit 105 disposed between the common address/data buses and the CPUb address/data buses to exclusively control accesses from the CPUa and the CPUb to a device connected to the common address/data buses and connect the CPUb adress/data buses to the common address/data buses only when the CPUb is permitted to access the device connected to the common address/data buses.

Abstract: A computer-implemented method is disclosed for use in a computer system. The method includes: (A) receiving an indication of a first hotplug event for a first operating system executing in the computer system; (B) identifying, among a plurality of hotplug handling methods, a first hotplug handling method associated with the first operating system; and (C) handling the first hotplug event using the first hotplug handling method.