Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Abstract: A sigma delta (SD) pulse-width modulation (PWM) loop includes a loop filter implementing a linear transfer function to generate a loop filter signal, wherein the loop filter is configured to receive an input signal and a first feedback signal and generate the loop filter signal based on the input signal, the first feedback signal, and the linear transfer function; and a hysteresis comparator coupled to an output of the loop filter, the hysteresis comparator configured to receive the loop filter signal and generate a sigma delta PWM signal based on the loop filter signal, wherein the first feedback signal is derived from the sigma delta PWM signal.

Abstract: A vehicle analog comparator circuit for communication interfaces designed to detect an actuation of an actor. The circuit comprises a unit for producing a supply voltage for supplying the actor, a unit for producing a reference voltage to be compared with the supply voltage, a transistor input stage, a node point EDMx between the actor, the unit for producing a supply voltage and the transistor input stage, and a digital evaluation unit to process the output signal from the transistor input stage such that whether or not the actor is actuated is detected. The transistor input stage comprises a transistor circuit with a first transistor is connected to the node point EDMx, and a second transistor connected to the reference voltage. A collector resistance for limiting the collector current of the second transistor, as well as a base resistance for the two transistors. Alternatively, a current mirror is provided.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

Abstract: A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: A shift register and a gate driver circuit are provided. The shift register includes an input unit, an output unit, an electrostatic discharge unit and a reset unit. The input unit provides an input signal. The output unit is coupled to the input unit and a gate output terminal. The output unit outputs an output signal through the gate output terminal according to the input signal. The electrostatic discharge unit is coupled to the output unit. After the gate output terminal outputs the output signal, the electrostatic discharge unit pulls down a voltage of the gate output terminal according to a low gate voltage. The reset unit is coupled to the input unit and the output unit. After the electrostatic discharge unit pulls down the voltage of the gate output terminal, the reset unit resets a voltage of a bootstrap node.

Abstract: A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T1, associated with a first current, IG_high; a second time period, T2, associated with a second current, IG_low; wherein: the first current of the driver waveform, IG_high, is larger than the second current of the driver waveform, IG_low; and the first time period, T1, has a first duration and the second time period, T2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.

Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.

Abstract: To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

Abstract: An integrated circuit (IC) includes: an input terminal; an output terminal; a first reference voltage terminal and a second reference voltage terminal; a high-side power switch coupled between the first reference voltage terminal and the output terminal; a low-side power switch coupled between the output terminal and the second reference voltage terminal; a first combinational logic and a second combination logic that are coupled to the input terminal; a first driver coupled between the first combinational logic and the high-side power switch; a second driver coupled between the second combinational logic and the low-side power switch; and first comparators coupled to the second combinational logic, where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch with a first threshold and a second threshold.

Abstract: An integrated circuit comprises a power input, digital logic circuitry, a plurality of charge stores, and obscuring circuitry. The charge stores are configured to receive power from the power input, are distributed through the digital logic circuitry and are capable of providing power to the digital logic circuitry. The obscuring circuitry is configured to obscure electromagnetic emissions associated with flow of current in current loops between the plurality of charge stores and the digital logic circuitry by switching between a plurality of different charge store activation patterns, wherein each charge store activation pattern describes a different selection of one or more of the plurality of charge stores providing power to the digital logic circuitry at a given time.

Abstract: A skyrmion logic gate is provided. The logic gate comprises a first track configured for propagation of magnetic skyrmions and a second track configured for propagation of magnetic skyrmions. A junction links the first and second tracks. A continuous current flows through the logic gate, wherein skyrmions propagate due to the current.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A shift register circuit includes a first input sub-circuit, an output sub-circuit and an output control sub-circuit. The first input sub-circuit transmits a signal received at a second signal input terminal to a pull-up node. The output sub-circuit transmits a signal received at a first clock signal terminal to a shift signal output terminal, and transmits a signal received at an output signal transmission terminal to a first scan signal output terminal. The output control sub-circuit transmits a signal received at a chamfering signal terminal to the first scan signal output terminal in a predetermined time before the first scan signal output terminal stops outputting the signal from the output signal transmission terminal. The chamfering signal terminal transmits a signal with a voltage amplitude within a variation range of a voltage amplitude of a signal of the first scan signal output terminal.

Abstract: A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.