Abstract: A slew rate boosting circuit, a source driver chip and a display device are provided in the present disclosure. The slew rate boosting circuit comprises: a first latch configured to receive and store first data; a second latch configured to receive and store second data, the second data being next to the first data; a first level shifter; an amplifier; and a slew rate boosting module configured to receive a high voltage data signal as current input data, and adjust a slew rate of an output stage of the amplifier according to a value of a specified bit of the first data, a value of a specified bit of the second data and the current input data.

Abstract: The embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit and a display apparatus. The shift register comprises an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal; an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal.

Abstract: A reliability detection device includes a control circuit, oscillator circuits, and an output circuit. The control circuit is configured to generate enable signals according to a mode signal. The oscillator circuits output oscillating signals, in which each of the oscillator circuits is configured to generate a corresponding oscillating signal in the oscillating signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillating signal according to a corresponding enable signal in the enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit. The output circuit is configured to output a detection signal according to the oscillating signals when the mode signal has the second logic value, in which the detection signal is to indicate a reliability of the functional circuit.

Abstract: Disclosed is a dual clock signal to pulse-width modulated signal conversion circuit, comprising: a first counter, an input end of which inputs a first clock signal, and an output end of which outputs a divided signal; an edge reset circuit, an input end of which inputs the divided signal, the output end of which outputs a first reset pulse signal and a second reset pulse signal, the first reset pulse signal being configured for resetting a second counter, and the second reset pulse signal being configured for resetting a third counter; a second counter, an input end of which inputs the second clock signal and the first reset pulse signal, and an output end of which outputs the first pulse-width modulated signal; a third counter, an input end of which inputs the second clock signal and the second reset pulse signal, and an output end of which outputs the second pulse-width modulated signal; a logic processing circuit, an input end of which inputs the first pulse-width modulated signal and the second pulse-widt

Abstract: A duty cycle correction circuit (DCCC) for a multi-modulus frequency divider, the DCCC comprising: a corrector chain comprising a plurality of flip-flops each configured to receive one of the internal signals; and at least one delay selection logic element, each configured to receive an output signal from different ones of the flip-flops and the output of each delay selection logic element is based on the received output signal and the division factor; the DCCC is configured such that: a first state change in its output signal is defined by a transition to a first logic state of one of the internal signals; and a second state change in its output signal is based on a transition to a second logic state of one of the internal signals after a delay period, wherein the duty cycle of the output signal is based on the delay period.

Abstract: A switch circuit is provided. The switch circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control end, a first output end, and a first input end. The first input end receives a first input signal whose logic level is one. The first P-type control transistor is coupled to the first input end and the first control end. The first P-type control transistor includes a second control end. The second control end receives a second input signal whose logic level is zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, the first input signal is transmitted to the first control end of the P-type transistor switch to turn off the P-type transistor switch.

Abstract: An electromagnetic interference suppression circuit, a driving method thereof, and an electronic apparatus are provided. In the electromagnetic interference suppression circuit, a signal generating sub-circuit may generate a plurality of parallel target sequence signals, each with a period greater than a period threshold and a quantity of target sequence signals greater than a quantity threshold; and a frequency generating sub-circuit may output a frequency-jittered drive signal, for driving a switch mode power supply to operate, to the switch mode power supply under the control of the plurality of parallel target sequence signals.

Abstract: An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period of low voltage. The present invention includes several major advantages. One advantage is that the code to execute the method is very lightweight. Another advantage is that the signals require no synchronization source. The signals of the present invention function as their own synchronization.

Abstract: A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

Abstract: A scan driver includes a plurality of stages, each including a first input part configured to transfer an input signal to a first set node in response to a second clock signal, a second input part configured to transfer a first clock signal to a first reset node in response to the input signal and the second clock signal, a first output part configured to output a third clock signal as a respective scan signal in response to a voltage of a second set node, a second output part configured to output a concurrent driving signal as the respective scan signal in response to a voltage of a second reset node, a first stress relieving transistor connected between the first set node and the second set node, and a second stress relieving transistor connected between the first reset node and the second reset node.

Abstract: A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

Abstract: In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

Abstract: A shift register unit circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, and a voltage regulating sub-circuit. The input sub-circuit receives an input signal from a signal input terminal to control a potential of a pull-up node. The pull-up sub-circuit outputs a gate driving signal to an output terminal under control of the potential of the pull-up node and a signal from a first signal terminal. The pull-down control sub-circuit conducts a pull-down node with a first node under control of a signal from the second signal terminal. The pull-down sub-circuit conducts the pull-up node with the first node and the turn-down signal terminal with the output terminal under control of a potential of the pull-down node. The voltage regulating sub-circuit conducts the first node with the turn-down signal terminal under control of a potential of the first node.

Abstract: One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

Abstract: A hubodometer for attachment to a wheel hub comprising an outer housing enclosing equipment for measuring distance travelled based on the wheel hub's number of revolutions, and a NFC-based communications link for transmitting to an external unit data related to the measured distance and for receiving operational data such as the diameter of the vehicle's wheel, and the position of the hub to which the hubodometer is attached. The equipment comprises a first electronic assembly conjoined with the outer housing and a second assembly comprising an anti-rotation pendulum provided with two permanent magnets of opposing polarities, the positions of which subtend an angle smaller than 180 degrees. The first electronic assembly comprises a bipolar Hall sensor moving in a circular path that traverses North and South fields of the magnets, whose output signal is a rectangular wave in which different mark-to-space ratios are associated with forward or reverse travel direction.

Abstract: The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates.

Abstract: The present invention is directed to a frequency synthesizer with an improved architecture that eliminates a VCO and a method to build frequency synthesizers for generating high-frequency signals with low phase noise, low spurious, extremely fast switching speed and fine frequency resolution. The synthesizer provides significant improvement in performance, phase noise, switching speed, power, size and cost reduction.

Abstract: A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.