Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.

Abstract: A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

Abstract: A comb signal generator that includes at least two signal sources that each provide a signal, wherein the signals provided by the at least two signal sources are shaped similarly. The com signal generator also has a combining circuit connected with the at least two signal sources, wherein the combining circuit is configured to combine the signals provided by the at least two signal sources, thereby generating a combined signal. Further, the com signal generator includes a clipping circuit connected with the combining circuit, wherein the clipping circuit is configured to receive and process the combined signal, thereby generating a comb signal. Further, a method of providing a phase and amplitude reference is described.

Abstract: A serializer clock delay optimization system comprising a multiplexer configured to receive two or more low-rate data signals and a multiplexer control signal. The multiplexer generates a full-rate data signal by combining the two or more low-rate data signals such that the multiplexer control signal determines sampling time of the low-rate data signals. A data monitor monitors and evaluates the full-rate data signal to generate a quality value representing the quality of the full-rate data signal. The quality of the full-rate data signal is based on the accuracy of the sampling time of the low-rate data signals. A delay controller processes the quality value to generate a delay control signal or value. A delay receives a clock signal and the delay control signal or value. Responsive to the delay control signal or value, the delay modifies the timing of the clock signal to create the multiplexer control signal.

Abstract: A method for active gate driving a switching circuit, wherein: a characteristic of a waveform controlled by the switching circuit is represented by a function mapping an input variable to an output metric, and wherein: the input variable comprises: a design variable having a first set of possible values; and an environmental variable having a second set of possible values, wherein the environmental variable is observable but not controllable. The method comprising: performing Bayesian optimisation on the function to generate a model of the function, wherein a next value of the design variable for evaluating the function is selected based on values of an acquisition function associated with a predicted value of the environmental variable; determining a first value of the design variable that optimises the model of the function; and controlling the switching circuit according to the first value of the design variable.

Abstract: An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

Abstract: A pseudo-random sequence generator for use within a universal lidar system and its corresponding method of operation. The pseudo-random sequence generator uses synchronized shift registers that are in series Binary adders are provided. The signal output of each of the shift registers is tapped and directed to the binary adders. High-speed switches are provided between the shift registers and the binary adders. The switches are programmed to connect only two of the shift registers to the binary adders for each of the pseudo-random patterns being generated. The binary adders generate an output signal that is received by the first shift register. The signal propagates through all the shift registers to the last shift register. The last shift register outputs a pseudo-random sequence.

Abstract: A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.

Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

Abstract: Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During the standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During the standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

Abstract: A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

Abstract: A power switching circuit includes a first switch circuit, a second switch circuit, a control circuit, and a driver circuit. The first switch circuit receives a first power voltage and coupled to an output terminal. The first switch circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switch circuit receives a second power voltage and coupled to the output terminal. The second switch circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit generates a control signal according to an output voltage at the output terminal, a power state signal, and one of the first power voltage and the second power voltage. The driver circuit generates a first driving signal or a second driving signal according to the control signal to control the first switch circuit or the second switch circuit.

Abstract: A semiconductor relay device includes a conversion circuit configured to receive an input signal from outside and pass a first current to a first node based on the input signal. A zener diode has an anode coupled to a second node and a cathode coupled to the first node. A resistor is coupled between the second node and a third node. A number n of diodes are serially coupled. A thyristor has an anode coupled to the first node, a cathode coupled to the second node, and a control terminal coupled to the third node. A transistor has a gate coupled to the first node. An anode of a diode at a first end of the n diodes is coupled to the first node, and a cathode of a diode at a second end of the n diodes is coupled to a third node.

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Abstract: A method of stabilizing data of digital signals is provided. The method includes steps of: (a) determining whether or not next input data is larger than previous output data, if yes, adding a base value to a trend value and then performing step(c), if no, performing step(b); (b) determining whether or not the next input data is smaller than the previous output data, if yes, subtracting the base value from the trend value and performing step(c), if no, performing step(c); (c) determining whether or not the trend value is larger than a positive threshold, if yes, subtracting a trend correction coefficient from the previous output data, if no, performing step(d); and (d) determining whether or not the trend value is smaller than a negative threshold, if yes, adding the trend correction coefficient to the previous output data; if no, outputting the previous output data.

Abstract: The present specification provides a display apparatus allowing brightness of a display panel to be more finely controlled as compared with the related art. The display apparatus according to the present specification includes a display panel in which a plurality of pixels are arranged in m×n, and K shift register units configured to sequentially output pulse signals having a width adjusted to adjust brightness of the display panel to m horizontal pixel lines, wherein each of the shift register units includes m main flip-flops and m?1 sub-flip-flops connected between the in main flip-flops.

Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The first time delay circuit has a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal. The second time delay circuit has a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.

Abstract: A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

Abstract: This document discloses a comparator that is configured to control dead-time between two or more switching transistors. In particular, it is disclosed that the comparator is configured to generate a suitable delay between the switching “OFF” of a transistor and the switching “ON” of another transistor so that the amount of shoot through current flowing between these two transistors are greatly minimized.

Abstract: Embodiments of the present disclosure provide a shift register unit and a method foe driving the same, a gate driving circuit, and a display device. The shift register unit includes: a control circuit coupled to an input signal terminal, a clock signal terminal, and an output control terminal, and configured to provide an output control signal to the output control terminal based on a signal from the input signal terminal and a signal from the clock signal terminal; and an output circuit coupled to the output control terminal, an output signal terminal, and a threshold voltage control terminal, and configured to provide an output signal to the output signal terminal under control of a potential at the output control terminal, and adjust a threshold voltage of at least one of a plurality of transistors in the output circuit under control of a signal from the threshold voltage control terminal.