Abstract: A frequency measurement apparatus includes: a measurement period setting circuit that sets a measurement period based on a reference clock signal; a first counter circuit that counts the number of pulses of the reference clock signal in a period based on an input signal during the measurement period; a second counter circuit that counts the number of pulses of the input signal during the measurement period; a first frequency calculation circuit that calculates a first frequency; a second frequency calculation circuit that calculates a second frequency; and a frequency selection circuit that selects the first frequency or the second frequency as a frequency of the input signal.

Abstract: The present disclosure relates to a shift register circuit and a drive method thereof, a gate drive circuit, and a display panel. The shift register circuit comprises a second reset circuit, and a reset operation is performed for a first node and a signal output terminal by the second reset circuit during an off stage of the display panel.

Abstract: Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

Abstract: According to an embodiment, a semiconductor device includes a differential input circuit suitable for receiving first and second input signals respectively inputted to first and second input transistors, and outputting an output signal; a comparison circuit suitable for generating a first judge signal by comparing the output signal with a first comparison voltage, and generating a second judge signal by comparing the output signal with a second comparison voltage, in a calibration mode; an offset control circuit suitable for adjusting coarse codes and fine codes, according to the first and second judge signals; and an offset adjusting circuit suitable for adjusting a drivability of each of the first and second input transistors by a first strength, according to the coarse codes, and adjusting the drivability of each of the first and second input transistors by a second strength smaller than the first strength, according to the fine codes.

Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

Abstract: A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.

Abstract: A lightning strike counter and a lightning strike counting method are disclosed. The lightning strike counter includes a lightning strike input circuit, a bipolar waveform generating circuit, and a counting circuit. The lightning strike input circuit receives a lightning strike signal from a first lightning strike input end and a second lightning strike input end. The bipolar waveform generating circuit outputs a bipolar waveform signal from a bipolar waveform output end to the counting circuit in response to the lightning strike input circuit receiving the lightning strike signal. The counting circuit outputs a counting output signal from a counting output end in response to receiving the bipolar waveform signal from a counting input end.

Abstract: The present disclosure provides a pre-emphasis circuit, method and display device, and belongs to a field of display driving. The pre-emphasis circuit according to the disclosure can determine whether to output a pre-emphasis voltage corresponding to grayscale of current input data via an input terminal of an amplifier according to data input to a data terminal by adding an amplifier input pre-emphasis module. Rapid conversion of output voltage can be realized without increasing the quiescent current of the amplifier, while the stability of temperature of the IC is ensured.

Abstract: The embodiments of the present disclosure propose a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register includes: a scanning circuit configured to generate a first signal for causing a gate driving signal output by the shift register to have a row shift portion during a scanning period; a sensing circuit configured to generate a second signal for causing the gate driving signal to have a frame shift portion during a blanking period; and a random shift circuit electrically coupled to the scanning circuit and the sensing circuit respectively, and configured to generate the gate driving signal having the row shift portion and randomly having the frame shift portion based on the first signal and the second signal.

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

Abstract: An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.

Abstract: A method and apparatus for generating a drive signal for driving a resolver sensor are provided. The method and apparatus implement a drive signal to be input to a resolver sensor. The method and apparatus perform counting in association with an incoming square wave signal and implement a drive signal after confirming that a specific point corresponding to a preset condition of the incoming square wave signal arrives.

Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Abstract: A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.

Abstract: The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Abstract: A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

Abstract: A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.