Patents Examined by Tuan Thai
  • Patent number: 9972393
    Abstract: According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 15, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: Avigdor Segal
  • Patent number: 9965200
    Abstract: In large complex multi-path storage environments, knowing there is a problem is extremely valuable. Example embodiments of the present invention include a management framework that provides an easy to use and read graphical perspective that allows analysis of faults in a multi-path storage environment. The architecture is not only responsive, scalable, and robust, but also provides “middleware” services to a broad spectrum of enterprise management applications whose domains may extend beyond storage path management.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 8, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Todd R. Gill, James A. Perreault, John S. Neil, Vinay S. Sachdev, Harold M. Sandstrom, Reshma P. Chitre, Eric A. Covino, Bradley A. Bowlin
  • Patent number: 9965402
    Abstract: In some embodiments, a memory initialization detection process includes detecting a read instruction of a program, where the read instruction addresses a particular memory location, and where data corresponding to the particular memory location is cached in a particular cache line of a memory cache. The memory initialization detection process further includes determining, based on metadata stored in the memory cache, that a section of the particular cache line does not store valid data of the program. The memory initialization detection process further includes obtaining validity data from the section of the particular cache line. The memory initialization detection process further includes determining, based on the validity data, whether the read instruction is authorized to proceed.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 8, 2018
    Assignee: Oracle International Business Machines Corporation
    Inventor: Darryl J. Gove
  • Patent number: 9959210
    Abstract: In various embodiments, a storage device includes a magnetic media, a cache memory, and a drive controller. In embodiments, the drive controller is configured to establish a portion of the cache memory as an archival zone having a cache policy to maximize write hits. The drive controller is further configured to pre-erase the archival zone, direct writes from a host to the archival zone, and flush writes from the archival zone to the magnetic media. In embodiments, the drive controller is configured to establish a portion of the cache memory as a retrieval zone having a cache policy to maximize read hits. The drive controller is further configured to pre-fetch data from the magnetic media to the retrieval zone, transfer data from the retrieval zone to a host upon request by the host, and transfer read ahead data to the retrieval zone to replace data transferred to the host.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 1, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Munif F. Farhan, William F. Sauber, Dina A. Eldin
  • Patent number: 9959067
    Abstract: An individual block health metric value calculated for each of a plurality of blocks from a combination of factors including at least program-erase cycle count and error rate is used to order the plurality of blocks in order of block health metric values in an ordered list. Subsequently, a block may be selected for use according to a position of the block in the ordered list.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: May 1, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Niles Yang, Jianmin Huang, Swati Bakshi
  • Patent number: 9959078
    Abstract: Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 1, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Grishma Shah, Jack Frayer, Aaron Olbrich, Chang Siau, Vidyabhushan Mohan, Gopinath Balakrishnan, Robert Ellis
  • Patent number: 9946894
    Abstract: Provided is a data processing method in a data processing device that is connected to an external storage device and that is equipped with a storage device, the method including: receiving a writing instruction to store first data in the storage device; dividing the first data into multiple pieces of division data; storing at least one or more of the pieces of division data in the external storage device; and storing second data different from the first data in the storage device, in which the second data is associated with the first data and the multiple pieces of division data. With the data processing method, security in data management can be improved.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsurou Kitazawa, Kouji Mutou, Minoru Ozaki, Yutaka Iyoki, Tadaomi Asou
  • Patent number: 9940205
    Abstract: A System, Computer program product, and computer-executable method for providing a user access to an image of data storage, wherein the data storage is managed by a data protection appliance (DPA), the System, Computer program product, and computer-executable including receiving a request for the image of data storage, wherein the image requested is the data storage at a Point in Time (PiT), creating a virtual image of data storage using a difference journal, wherein the virtual image provides the user with access to data within the requested image at the PiT, and providing access to the virtual image.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Assaf Natanzon
  • Patent number: 9941007
    Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 10, 2018
    Assignee: Thstyme Bermuda Limited
    Inventors: Charles I. Peddle, Martin Snelgrove, Robert Neil McKenzie, Xavier Snelgrove
  • Patent number: 9940042
    Abstract: Each of a plurality of storage systems in a distributed storage system is provided with: a strong-consistency-control processor which controls data synchronization that ensures consistency of duplicated data; a weak-consistency-control processor which controls data synchronization that does not necessarily ensure consistency of the duplicated data; an access-switching processor which determines a redundancy number corresponding to the number of storage systems having duplicated data stored thereon, selects in accordance with the characteristics of the duplicated data and the position of a terminal issuing the I/O request, storage systems of a number corresponding to the redundancy number, and selectively determines, as the control for the data synchronization, one from among the strong-consistency-control processor, the weak-consistency-control processor, and consistency control unnecessary; and an I/O processor which executes, on the basis of the determined control for the data synchronization, the I/O reque
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 10, 2018
    Assignee: HITACHI, LTD.
    Inventor: Masakuni Agetsuma
  • Patent number: 9933959
    Abstract: A method and computer program product are provided to ensure a timely secure data erase by comparing a number of secure data erase operations in a queue to a maximum queued threshold, the secure data erase operations corresponding to physical volumes to be secure data erased. In response to determining that the number of secure data erase operations in the queue is greater than the threshold, an average time to a secure data erase deadline is determined. The average time to the secure data erase deadline is compared to a predefined expiration threshold. In response to determining that the average time to the secure data erase deadline is less than the predefined expiration threshold, at least one additional resource is allocated to perform the queued secure data erase operations for completing the secure data erase operations prior to the secure data erase deadline.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gregory Tad Kishi, Mark Allan Norman, Laura Jean Ostasiewski, Christopher Michael Sansone
  • Patent number: 9933970
    Abstract: A method and system for deduplicating data for a data storage system using similarity determinations are described. A tape library is arranged in a hierarchy of tape groups and tape plexes. Tape groups are an admin visible entity and are comprised of multiple tape plexes (at least equal to the number of replicas in a tape group). Tape plexes in turn comprise multiple tape cartridges. Data files and objects received within a time period are initially staged in a disk cache where they are logically segregated into cliques based on their expected deduplication ratios. These cliques are then evaluated for the amount of duplication they have with data existing in tape plexes. Based on the number of replicas being written, the top few tape plexes are selected from within the tape group. The cliques are deduplicated with data on the selected tape plexes, compressed, and written to tape.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 3, 2018
    Assignee: NetApp, Inc.
    Inventors: Atish Kathpal, Giridhar Yasa
  • Patent number: 9927983
    Abstract: Methods, systems, and computer readable media for intelligent fetching of storage device commands from submission queues are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes collecting submission queue command statistics; monitoring resource state of the data storage device. The method further includes using the submission queue command statistics and the resource state to select a submission queue from which a next data storage device command should be fetched. The method further includes fetching the command from the selected submission queue. The method further includes providing the command to command processing logic.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Shay Benisty, Noga Harari Shechter, Amir Segev, Tal Sharifie
  • Patent number: 9921773
    Abstract: Deduplicated data storage is provided by presenting a virtual volume mapped by a translation table to a physical volume of a physical data storage system. The translation table maps sets of ranges of duplicate data blocks of the virtual volume to corresponding individual ranges of shared data blocks of the physical volume. A hash table for identifying duplicate data is indexed by a portion of a hash value calculated from newly written data blocks, and has entries each identifying an address alignment of the corresponding data block. In operation, existing entries are replaced with new entries for colliding data blocks having better address alignment, promoting wider address-space separation of the entries. Upon occurrence of a hit in the hash table, for a given data block in a range of newly written data blocks, data blocks of the range are compared to corresponding blocks in a range identified by the hit to maximize a size of a region to be identified by the translation table as duplicate data.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 20, 2018
    Assignee: Citrix Systems, Inc.
    Inventor: Ivan Georgiev
  • Patent number: 9921757
    Abstract: A plurality of programmable logic blocks are programmed in a first configuration to perform one or both of an access function and a management function with respect to a plurality of non-volatile memory modules. A high data transfer rate connection is provided to an external random access memory device, wherein said at least a subset of said programmable logic blocks are programmed in said first configuration to perform one or both of said access function and said management function at least in part using data sent via a communication interface, wherein the communication interface is coupled to at least a subset of said programmable logic blocks.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Kevin Rowett
  • Patent number: 9921765
    Abstract: Systems and methods create partial snapshot for a volume. Files and folders are identified for inclusion in the partial snapshot. In response to writing updated data to the volume, a volume snapshot layer can determine of the updated data is associated with a file or folder in the partial snapshot. If the file or folder is included in the partial snapshot, original data at the volume location is read from the volume and written to the partial snapshot.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 20, 2018
    Assignee: AVAST SOFTWARE S.R.O.
    Inventor: Petr Kurtin
  • Patent number: 9916255
    Abstract: Technologies are generally described for methods and systems effective to store data in a memory module. The memory module may include a volatile portion and a non-volatile portion. The methods may comprise receiving, by a processor, a request to store the data. The request may include an indication of a virtual address. The methods may further include determining, by the processor, a persistency of the data based on the virtual address. The methods may further include performing a first operation of identifying a particular portion of the memory module based on the virtual address. The methods may further include generating a command to store the data in the particular portion of the memory module. The methods may further include controlling the operating system to perform a second operation of updating a translation lookaside buffer to indicate the persistency of the data.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 13, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Yan Solihin
  • Patent number: 9910608
    Abstract: A storage system includes a storage unit and a control unit. Data is stored in the storage unit. The control unit performs replication of data that is updated, based on the frequency with which the data is updated. The control unit may include a frequency detection unit, a policy management unit, and a replication performance unit. The frequency detection unit detects the update frequency with which the data is updated, by detecting the number of times that the data is updated. The policy management unit determines a replication policy for the data based on the update frequency with which the data is updated. The replication performance unit performs replication of the updated data based on the replication policy.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: March 6, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Koji Muramatsu
  • Patent number: 9910619
    Abstract: A solid state drive includes a dual buffer for buffering incoming write data prior to committal to a non-volatile memory. The buffer is operated to provide a temporary backup of dirty data pending successful completion of a host transfer. The dual buffer may be operated as a primary buffer and a secondary buffer. The primary buffer may be used as the default buffer during normal operation. The secondary buffer is written to during a host transfer that is a cache write to dirty data. A copying process may be used to copy data between the primary and the secondary buffer to preserve the backup data pending successful completion of the host transfer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Christopher Delaney, Gordon Waidhofer, Leland Thompson, Ali Aiouaz
  • Patent number: 9904624
    Abstract: In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 27, 2018
    Assignee: Apple Inc.
    Inventors: Tyler J. Huberty, Stephan G. Meier, Khubaib Khubaib