Abstract: A method and apparatus for an innovative object oriented framework system. The system uses an innovative framework architecture to provide concurrent access to a framework application by multiple users. The users can collaborate over the application and jointly produce a finished product. Model tracking is used to track commands and apply them in a consistent manner throughout the system.

Abstract: Dedicated registers are arranged in a status LCD control gate array connected to a system bus, and the dedicated registers or register group and a keyboard controller are connected through a keyboard interface bus. The keyboard controller has two ports for communicating with a CPU. The keyboard controller transfers existing commands released to an application program or the like and transmits normal key data through the system bus. The keyboard controller transmits hot key data and transfers a command for realizing any other special function through the keyboard interface bus and the dedicated registers.

Abstract: A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

Abstract: A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched.

Abstract: A circuit for interconnecting electrical components in a stacked arrangement by the use of connector elements in which a substantially continuous bus is formed by the connector elements and the components to conduct signals between the components in the arrangement. The circuit and arrangement include identifier circuitry for automatically assigning an identifier to each electrical component in the stack and terminating circuitry for selectively establishing terminating connections between a terminal electrical component of the stack and the substantially continuous signal bus. The identifier circuitry and the terminating circuitry can be implemented by programmable array logic located in each electrical component.

Abstract: Dedicated registers are arranged in a status LCD control gate array connected to a system bus, and the dedicated registers or register group and a keyboard controller are connected through a keyboard interface bus. The keyboard controller has two ports for communicating with a CPU. The keyboard controller transfers existing commands released to an application program or the like and transmits normal key data through the system bus. The keyboard controller transmits hot key data and transfers a command for realizing any other special function through the keyboard interface bus and the dedicated registers.

Abstract: A method for the operation of a computer system controlled by a real-time operating system, which computer system processes interrupt signals. Upon the occurrence of an interrupt signal, the computer system interrupts a program that is to be processed at that time. The acceptance of further interrupt signals is blocked, and an interrupt routine belonging to this interrupt signal is called. During the processing of this interrupt routine, a first part of the program parameters of the program that is interrupted upon the occurrence of the interrupt signal is intermediately stored, and at least one datum concerning the interrupt signal is stored in an interrupt memory. A branching takes place from the interrupt routine to an interrupt management routine (IVR), whereby the acceptance of further interrupt signals is again cleared during the processing of the IVR.

Abstract: A bus translator is provided to translate the internal bus structure of a self-contained processor system to a system bus which is easily compatible with a plurality of different external components. In particular, the bus translator translates the packetized multiplexed internal bus to a de-multiplexed bus. The translator further provides the ability to add wait states to the transactions in order to accommodate slower memories and devices coupled to the system bus. Furthermore, the translator accommodates bus burst logic by providing an auto-increment addressing capability. In addition, as the processor operates on 32-bit words and coupled devices may operate on a smaller word size, the bus translator of the present invention provides a byte enable register file for performing byte operations within the 32-bit word operations of the system. Finally, the bus translator also provides accurate parity generation and checking on a byte basis.

Abstract: A system for managing power consumption of a computer by communicating power management events to a removable device of the computer. A device removal signal is transmitted to a device controller for the removable device in response to a power management event and while the device is installed within a socket of the computer. This device removal signal can provide notice of a power state change for the device, such as the interruption of electrical power to that device. This power state change is communicated by the device controller to a device driver in response to the device removal signal. Electrical power to the device is terminated in response to the power management event. A device insertion signal is transmitted to the device controller in response to another power management event and while the device remains installed within the socket. This device insertion signal provides notice of another state change for the device.

Abstract: A computer system combines a portable computer and a detachable palm rest containing a backup battery. When the palm rest is attached to the portable computer, power control circuitry within the computer provides automatic switching between the primary battery in the computer and the backup battery in the palm rest when the active battery becomes low. The power control circuitry also recharges the standby battery whenever the computer is plugged into external power. Power monitoring circuity displays the status of the standby battery on an indicator built into the palm rest.

Abstract: Method and apparatus in a data processing system (10) for determining wait states on a per cycle basis. The present invention provides a wait state value (39) to a data processing system (10) indicating the number of wait states for each bus cycle. In one embodiment, a wait state pulse (81) is provided by data processing system (10), during which the wait state value (39) is provided to data processing system (10) by way of data bus (82). In response to the wait state value (39), data processing system (10) inserts a number of wait states corresponding to the wait state value (39) during the present bus cycle. In one embodiment of the present invention, a chip select signal (73) is combined with a portion of the address (83) to further partition the address range of the chip select signal (73).

Abstract: A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a validity checker, and at least one processor interface. The validity checker monitors the state of each interrupt request as it is processed through the interrupt controller. The interrupt request is canceled if the interrupt request becomes invalid. Alternatively, the programmable interrupt controller issues a spurious interrupt vector if the interrupt request becomes invalid after a CPU has responded.

Abstract: An electronic apparatus, process for its duplication, and arrangement for data transfer between two similarly constructed electronic apparatus is described in which the electronic apparatus has a microprocessor or microcontroller, a non-volatile memory, and an interface. The microprocessor or microcontroller, the non-volatile memory and other measures of the apparatus allow a data content of a certain memory component of a certain other apparatus to be simply transferred into the non-volatile memory. The apparatus thus has the ability to bequeath its data characteristics, or to duplicate itself. Further, a process is described for carrying out such a duplication. Assuming a second inventive electronic apparatus is built, a particular advantageous arrangement can be created in which a data record can be completely transferred from the memory of the first apparatus into the memory of the second apparatus. This data transfer is even beneficially possible when the second apparatus is partially defective.

Abstract: A plurality of video dynamic random access memory devices (VRAMs) distributed among low speed local area network ports of a distributed memory switching hub interconnecting heterogeneous local area networks operating at different transmission speeds for receiving, storing and forwarding frames of data. The distributed memory switching hub employs a distributed memory architecture in which VRAM devices located at each low speed LAN port of the distributed memory switching hub store frames of data received or to be forwarded. The VRAM device is comprised of serial access memory (SAM) coupled to and transmitting frames of data with a high speed internal data bus at the same speed of the data bus and dynamic random access memory (RAM) coupled to and transmitting frames of data with a low speed local area network at the same speed of the low speed local area network. The SAM and RAM operate asynchronously with respect to each other to provide simultaneous bidirectional transfer of frames of data between them.

Abstract: A data processing system including a bus (ISA, EISA), in which address lines (SA) and data lines (SD) are connected in parallel to a series of slots for receiving, each, any one of a plurality of available extension cards. Control lines of the bus are connected in parallel to the slots, except at least one specific control line (AEN, SMEMR#) operable to enable a slot by rendering accessible, through the bus, the circuits of a card inserted in the slot. The data processing system further includes means (A, S, 30) programmable through the bus for transmitting the state of the specific control line to predetermined slots.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in an n-dimensional modified non-binary hypercube. In a 4-dimensional modified non-binary hypercube embodiment, each node includes either processor memory elements on a single chip, each processor memory element having its own associated processing element, significant memory, and I/O, with each processor memory element supporting an external port. Pairs of ports are associated with each dimension, labeled X, Y, W, and Z. Eight nodes are connected in the X dimension to form a ring. Corresponding nodes from eight such rings are connected into rings in the Y dimension to form an 8.times.8 array of nodes, referred to as a cluster. Corresponding nodes of eight clusters are connected into ring (64 rings) in the Z dimension, forming an 8.times.8.times.8 array of nodes referred to as a "cluster ring".

Abstract: Circuitry for performing a memory block write is described. The memory block includes b block words, each block word having t block bytes. Each block byte has s bits of memory. Each block byte is associated with at least two associated mask value bits. A constant register has at least s.times.t bits of memory arranged as t constant bytes, each constant byte storing a constant value, each constant byte associated with one block of every block word. The block write circuitry includes control circuitry for selecting one of a normal write function and a block write function in accordance with a block write signal. When the block write function is selected, the control circuitry stores the associated constant value in every nonmasked block byte substantially simultaneously in accordance with a value of the associated mask value bits.

Abstract: An electronic computer system is formed of a control processor (1) and a plurality of processor elements (3.sub.1 -3.sub.n). Each of the processor elements (3.sub.1 -3.sub.n) has a control unit (30.sub.i) that processes instructions issued by the control processor (1) in the SIMD manner, a data-driven processing unit (31.sub.i) for performing arithmetic/logic operations and data transfering to a destination processor element of the processor elements (3.sub.1 -3.sub.n) through a packet transmission network (22) in a data-driven manner and a local memory (35.sub.i). The control processor (1) broadcasts instructions to set the data-driven processing unit (31.sub.i) in each of the processor elements (3.sub.1 -3.sub.n) contents that are to be performed in the data-driven manner. In each of the processor elements (3.sub.1 -3.sub.n), operations in the data-driven processing unit (31.sub.i) based on the data-driven manner are performed in parallel with setting of the data-driven processing unit (31.sub.i).

Abstract: An apparatus and method for displaying power management system (PMS) information in a portable computer includes a video random access memory (RAM) for storing the power management system (PMS) information as a preset data configuration. A keyboard controller outputs a signal corresponding to an operating state represented by a user key selection and a system interrupt signal. A power management system (PMS) controller outputs a corresponding signal after sensing a present charging/discharging state of the voltage of a battery. A real-time clock (RTC) stores data corresponding to the mode and level of the power management system (PMS) set during an initial set-up step of computer operation. A video controller reads the power management system (PMS) information stored in the video random access memory (RAM), and displays the information as a preset data configuration on a display unit when a corresponding key signal is output from the keyboard controller.

Abstract: A communication network for an industrial control system permits multiple masters and complex network topologies by transmitting data as packets through paths of nodes on the networks. The packets containing data are preceded by an OPEN message which pre-configured each node with the necessary information to process the stream of succeeding packets in an efficient manner and thus to reduce the necessary overhead in the transmission of each data packet. Each node receiving the OPEN message evaluates its resources and if those resources are insufficient to reliably handle the indicated packets, a message is returned to the originating node indicating that a connection cannot be formed.