Patents Examined by Valerie Darbe
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Patent number: 5627987Abstract: A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched.Type: GrantFiled: February 23, 1993Date of Patent: May 6, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Nozue, Mitsuo Saito, Kenichi Maeda, Shigehiro Asano, Toshio Okamoto, Shin Sungho, Hideo Segawa
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Patent number: 5617577Abstract: A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper.Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge.Type: GrantFiled: March 8, 1995Date of Patent: April 1, 1997Assignee: International Business Machines CorporationInventors: Thomas N. Barker, Clive A. Collins, Michael C. Dapp, James W. Dieffenderfer, Donald G. Grice, Billy J. Knowles, Donald M. Lesmeister, Richard E. Nier, Eric E. Retter, David B. Rolfe, Vincent J. Smoral
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Patent number: 5617576Abstract: An execution speed controller for controlling the effective processing rate of a microprocessor including an internal cache memory. In one embodiment, the execution speed controller monitors the activities of the microprocessor to determine when it is executing a section of code whose execution should be slowed. When such a determination is made, the execution speed controller periodically asserts at least one control input to the microprocessor. This periodically prevents the microprocessor from accessing the main memory and the internal cache memory, thereby slowing microprocessor execution. In this embodiment, only those software applications requiring slow down are effected. Newer software applications may not require this mode and may run at full speed. An alternate embodiment that does not require a triggering event is also described. In this embodiment, execution of all software applications is slowed down. This is referred to as the "compatibility" mode.Type: GrantFiled: February 7, 1995Date of Patent: April 1, 1997Assignee: Intel CorporationInventors: Edward L. Solari, Thomas A. Heckenberg, Subbarao Vanka
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Patent number: 5613135Abstract: Dedicated registers are arranged in a status LCD control gate array connected to a system bus, and the dedicated registers or register group and a keyboard controller are connected through a keyboard interface bus. The keyboard controller has two ports for communicating with a CPU. The keyboard controller transfers existing commands released to an application program or the like and transmits normal key data through the system bus. The keyboard controller transmits hot key data and transfers a command for realizing any other special function through the keyboard interface bus and the dedicated registers.Type: GrantFiled: August 16, 1993Date of Patent: March 18, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Sakai, Koichi Dewa, Hiroyuki Tsukada, Keiichi Uehara, Tohru Mamata, Yasuhiro Nishino, Hiroyuki Oda
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Patent number: 5604878Abstract: Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units.Type: GrantFiled: August 1, 1995Date of Patent: February 18, 1997Assignee: Intel CorporationInventors: Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert W. Martell, David B. Papworth
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Patent number: 5600847Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).Type: GrantFiled: June 7, 1995Date of Patent: February 4, 1997Assignee: Texas Instruments IncorporatedInventors: Karl M. Guttag, Keith Balmer, Robert J. Gove, Christopher J. Read, Jeremiah E. Golston, Sydney W. Poland, Nicholas Ing-Simmons, Philip Moyse
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Patent number: 5598569Abstract: A data processor (20) includes a nonvolatile memory system (25) which stores not only normal program memory (31), but also mask option bits (32), within a common array (30) of nonvolatile memory cells. A control circuit (40) of the nonvolatile memory system (25) detects when a central processing unit (21) is accessing the program memory (31). In response to either an end of reset signal or a refresh request signal, the control circuit (40) copies the mask option bits (32) into a volatile mask option register (44) only when the central processing unit (21) is not accessing the program memory (31). Otherwise, the control circuit (40) holds off the access to the mask option bits (32). The mask option register (44) provides signals to various circuits (28) to control their operation. Thus, the mask option bits (32) may be stored in nonvolatile form in the same array (30) as the program memory (31), enhancing reliability and reducing integrated circuit size.Type: GrantFiled: October 17, 1994Date of Patent: January 28, 1997Assignee: Motorola Inc.Inventors: Michael I. Catherwood, George L. Espinor
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Patent number: 5596766Abstract: A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which provide inputs to programmable selectors (POR, UCL, . . . ) for controlling implementation of logic functions of various types and functionality by a controllable logic function sub-network by routing through the sub-network, logic values and logic instructions originating externally of the PLD's. Each programmable logic device includes an AND logic array (FAND . . . ) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG . . . ) having inputs for receiving signals and generating sum term output signals (OF . . . ).Type: GrantFiled: February 16, 1995Date of Patent: January 21, 1997Assignee: Infinite Technology CorporationInventors: Earle W. Jennings, III, George H. Landers
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Patent number: 5592680Abstract: This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.Type: GrantFiled: February 21, 1995Date of Patent: January 7, 1997Assignee: Fujitsu LimitedInventors: Teruo Utsumi, Shigeru Nagasawa, Masayuki Ikeda, Naoki Shinjo, Masami Dewa, Haruhiko Ueno, Kazushige Kobayakawa, Kenichi Ishizaka
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Patent number: 5590350Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).Type: GrantFiled: November 30, 1993Date of Patent: December 31, 1996Assignee: Texas Instruments IncorporatedInventors: Karl M. Guttag, Keith Balmer, Robert J. Gove, Christopher J. Read, Jeremiah E. Golston, Sydney W. Poland, Nicholas Ing-Simmons, Philip Moyse
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Patent number: 5590345Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: May 22, 1992Date of Patent: December 31, 1996Assignee: International Business Machines CorporationInventors: Thomas N. Barker, Clive A. Collins, Michael C. Dapp, James W. Dieffenderfer, Donald G. Grice, Peter M. Kogge, David C. Kuchinski, Billy J. Knowles, Donald M. Lesmeister, Richard E. Miles, Richard E. Nier, Eric E. Retter, Robert R. Richardson, David B. Rolfe, Nicholas J. Schoonover, Vincent J. Smoral, James R. Stupp, Paul A. Wilkinson
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Patent number: 5579529Abstract: A method for the configuration of peripheral adapters in computer systems. The method examines a flag in a Configuration Space of the peripheral adapter to determine if user-selectable configuration options are required for the peripheral adapter. If the flag is set, then a configuration file is retrieved and interpreted to determine how the peripheral adapter should be configured and to determine how the configuration options should be presented to the user. Such configurations options may be conditional and based on previous user selections. Once the user's selections have been made, the method updates registers in the peripheral adapter with the selected option values.Type: GrantFiled: April 19, 1995Date of Patent: November 26, 1996Assignee: NCR CorporationInventors: Michael R. Terrell, Jeffery W. Kaisner, Jonathan D. Amsden, Thomas C. Burke, David K. Todd
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Patent number: 5560028Abstract: A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be executed in parallel are identified. The system includes a register for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags and group identification tags indicative of the pipeline to which they should be dispatched, and the group of instructions which may be dispatched during the same operation. The pipeline and group identification tags are used to dispatch the appropriate groups of instructions simultaneously to the differing pipelines.Type: GrantFiled: April 13, 1995Date of Patent: September 24, 1996Assignee: Intergraph CorporationInventors: Howard G. Sachs, Siamak Arya
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Patent number: 5560025Abstract: A method and apparatus for searching for a pattern of values indicating vacancy within a reservation station. The present invention includes a method and apparatus for search a deallocation vector of an instruction scheduler in order to locate, within one clock cycle, a pattern of the first vacancies within the instruction scheduler for storage of instruction information associated with several microprocessor instructions. The present invention advantageously locates four vacant entries of the deallocation vector which specify the first four vacancies within a reservation station of the instruction scheduler and may be utilized to locate the first four vacant entries as well. The present invention performs the above processing utilizing high speed parallel processing methods so that the entire searching, reporting and updating functions, with regard to the deallocation vector, can be completed within one clock cycle. Two embodiments of the present invention, a static and a dynamic embodiment, are presented.Type: GrantFiled: March 31, 1993Date of Patent: September 24, 1996Assignee: Intel CorporationInventors: Shantanu R. Gupta, James S. Griffith
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Patent number: 5548773Abstract: The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signals throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.Type: GrantFiled: March 30, 1993Date of Patent: August 20, 1996Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Sabrina E. Kemeny, Eric R. Fossum, Robert H. Nixon
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Patent number: 5537563Abstract: A processing system operates on data words each having first and second portions. A first memory stores the first portion of a first data word accessible by a first set of address bits received at first address inputs and a second set of address bits received at second address inputs, and stores the second portion of a second word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A second memory stores the first portion of the second data word accessible by a first set of address bits received at first address inputs and a second set of bits received at second address input, and stores the second portion of the first word accessible by the first set of address bits received at the first address inputs and a third set of address bits received at the second address inputs. A first access mode accesses a selected one of the first and second portions of both the first and second words.Type: GrantFiled: February 16, 1993Date of Patent: July 16, 1996Assignee: Texas Instruments IncorporatedInventors: Karl M. Guttag, Robert J. Gove, Richard Simpson
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Patent number: 5537642Abstract: A system for providing distributed control of a resource with centralized configuration management. A network of distributed workstations is provided for controlling a resource such as a large mainframe computer. Server workstations for applying control commands to the resource are attached to each resource, preferably through redundant connections. Remote client consoles are defined which may be connected to the server for control of that resource. Server and resource location and primary and fallback connection paths are maintained by a centralized control server. Upon client console request, the central control server causes the server workstation associated with a particular resource to establish a control session between the server and the client console. A record of each dynamic connection is maintained by the central control server. Upon failure of a client console, the server accesses central server fallback information and establishes a fallback connection with an operational client console.Type: GrantFiled: April 4, 1994Date of Patent: July 16, 1996Assignee: International Business Machines CorporationInventors: David A. Glowny, Jenngang Shih, Brian P. Carr
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Patent number: 5467465Abstract: A method to simplify the use of a plurality of identical processors connected in parallel. The method contains the steps of: (a) obtaining a computer system having a CPU and a plurality of identical processors connected in parallel, the processors are also connected to the CPU; (b) obtaining first and second clocks of different oscillation frequencies, wherein the first clock having a slower oscillation frequency than the second clock; (c) connecting the first clock to only one of the plurality of processors and connecting the second clock to the rest of the plurality of processors; and (d) instructing the CPU to check only the processor connected to the first clock, which is connected to the slower clock, for a ready signal, and instructing the CPU to proceed to next step if a ready signal is received from the processor connected to said first clock.Type: GrantFiled: November 17, 1993Date of Patent: November 14, 1995Assignee: UMAX Data System Inc.Inventor: Daniel Chen
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Patent number: 5457806Abstract: A LAN analyzer is applied to a computer system in which a plurality of computers are connected to a transmission line of a LAN, and which has a first operation mode wherein the plurality of computers execute a piece of information processing, while using a message passing through the transmission line and a second operation mode wherein the same operation as in the first operation mode is replayed.Type: GrantFiled: November 29, 1993Date of Patent: October 10, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Asako Kitamura
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Patent number: 5450597Abstract: A method and apparatus for ensuring that MIDI data stored in the subcode channel area of a compact disc is synchronized with the main channel audio of the compact disc. Synchronization problems have been created when transferring audio on a tape from an audio studio to a PCM 1630 tape which is to be used as a compact disc master resulting in a squashing or stretching of the audio data with respect to the MIDI data. One reason this can occur is because F-1 tape records and plays back at 29.97 frames per second while PCM 1630 tape records and plays back at 30 frames per second. The result is that even if the MIDI data and main channel audio data begin in sync, they lose sync during transfers and may drift apart linearly over time as well as be offset with respect to each other. The present invention corrects such synchronization problems by playback simulation, MIDI data/Main channel audio sync measurement and MIDI data adjustment.Type: GrantFiled: December 12, 1991Date of Patent: September 12, 1995Assignee: Time Warner Interactive Group Inc.Inventors: Walter R. Klappert, Michael Case