Abstract: An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag indicating a user-defined priority for that cache line The replacement mechanism comprises an apparatus for selecting a cache line with the lowest user-defined priority in a current set of cache lines, and apparatus (e.g. based on recency of usage) for choosing between cache lines of equal priority if there is more than one cache line with said lowest user-defined priority in the current set.

Abstract: Signalling apparatus are used for monitoring a clock signal from a system controller to a processor. If the clock signal is low, indicating that the processor is disabled, the signalling apparatus will place the cache memory in a "sleep" mode. Thus, the signalling apparatus allow a computer system, upon which the signalling apparatus is a part of, to lower its power consumption. If the computer system is a portable computer system, the signalling apparatus will lower power consumption thereby extending the lifetime of the portable computer's batteries.

Abstract: A data processing apparatus with a function of effecting a hang-up processing inhibits detecting retention of an access request as a hang-up, when the access request is accepted by a predetermined port. The apparatus includes a single time counting unit (76) provided in common for hang-up detection circuits (71 to 75). By this constitution, it is possible to reduce the number of hardwares, and to prevent an access request, which should not be detected as a hang-up, from being detected as a hang-up.

Abstract: An apparatus and method for computing population counts of large bit strings. The present invention utilizes carry-save adders to reduce the time required to perform a population count on an operand in a register. Because carry-save adders do not propagate carries they are inherently faster than full adders utilized in the prior art. Additionally, the present invention implements a novel method for computing population counts whereby the operand bit string is split into smaller blocks and multiple partial population counts are performed. These smaller partial population counts require less time to compute than a full population count over the entire operand bit string.

Abstract: A fully associative cache memory has a finite state machine which creates and maintains a linked list structure within the cache. This linked list structure allows the fully associative cache memory to be implemented in a structure other than a complex FIFO arrangement, as is typically required by systems of the prior art.

Abstract: In a shared memory multiprocessing computer system, multiple processors can cache copies of a shared data block in their local cache memories and independently modify their cached copies. The cached copies are later merged in a global memory with the shared data block. With each cached copy, a bitmask consisting of a plurality of flags associated with elements of the cached copy also is stored in the local memories. A local memory controller tracks which elements of the cached copies are modified by setting the bitmask flags associated with such elements. When merging, only modified elements of the cached copies are stored in the originating data block as indicated by the bitmask flags.

Abstract: A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also has a means for storing a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port.

Abstract: According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate line of data in the cache memory containing the faulty data. The present invention employs address detection circuitry which detects when a faulty data address stored in the tag RAM is presented during a microprocessor memory cycle and forces the valid bit for that faulty data to a predetermined logic level. When the valid bit associated with the faulty data is set to the predetermined logic level, the tag RAM generates a signal indicative of a "miss" condition. The "miss condition" is communicated to the microprocessor which must access the requested data from main memory, thus effectively bypassing the faulty data. The address detection circuitry of the invalidation circuitry may be expanded to handle any number of faulty data.

Abstract: A computer system having a bus providing signals for determining a next bus transaction; a processor connected to the bus; and a bus device connected to the bus, the bus device having a first register connected to the bus, a first gate connected to the first register through an output of the first gate, and, a multiple access inhibitor unit connected to a first input of the first gate through an output of the multiple access inhibitor unit.

Abstract: One page of image data is divided into six data streams of blocks data. First to sixth FIFO memories of a speed difference absorbing circuit absorb a difference between a transfer rate of the block data and a processing speed of the subsequent circuits. FIFO memories of a line delay circuit delay the respective block data such that delay times for the respective block data change step by step by a predetermined time. An order conversion circuit produces 4-line parallel image data by sequentially selecting the block data sent from the line delay circuit. Sync signals for the four respective lines are delayed step by step by a predetermined time.

Abstract: A hub featuring ports for attachment of stations to a LAN comprises concentration logic (14) for the handling of multiplexed incoming and outgoing Token-Ring and isochronous signal streams. The concentration logic comprises clock recovery logic (42) from incoming Token-Ring packet data stream (40), for regeneration of Differential Manchester encoded data on output (400), and recovering of Token-Ring clock (401). A cycle framing generator (43) receives a 125 us synchronization clock from the hub backplane (402), and the Token-Ring clock (401), and generates control signals (403) to each of the 10 ports. Each port is comprised of a port transmit interface (44), and a port receive interface (45). Data from a connected station is input (404) to port receive interface (45). Token-Ring packet Differential Manchester encoded data are output (406) to the next active port, specifically to its port transmit interface, along with a recovered strobe clock (405), while ISO data are output (407) to switch (46).

Abstract: A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a "normal" memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code.

Abstract: A cache which includes an integrated timing circuit through which the cache control passes thus allowing the timing of the storage circuit of the cache core to be adjusted.

Abstract: A message receiving method communicates a message among a plurality of computers in a parallel computer system, shortens a delay time in storing a received message in a user area of a memory, and realizes overlap between receipt of a message and execution by a processor. Each computer in the parallel computer system comprises a message buffer for temporarily storing the received message and a message handler for receiving a receive-a-message request from a processor of a computer to which it belongs. If the receive-a-message request arrives before the arrival of the message, the message handler directly transmits the received message to a user area specified by the receive-a-message request. During the transmission period, the message handler prevents the processor from accessing a portion in the user area to which the message has not been transmitted yet.

Abstract: A microprocessor controlled apparatus includes a microprocessor (2) with e.g. eight address lines (A,.sub.0,A.sub.1 . . . A.sub.7) on which signals may be applied by the microprocessor for selectively addressing a peripheral device coupled thereto, and a data device such as a LCD module (1) having data lines to which data signals may be applied for transfer into the data device. Four of the data lines (D.sub.0,D.sub.1,D.sub.2,D.sub.3) are coupled to a sub-set of the microprocessor address lines (A.sub.2,A.sub.3,A.sub.4,A.sub.5) excluding the two address lines (A.sub.0,A.sub.1) associated with the least significant bits. The signals on the sub-set of address lines are thus applied as data signals to the data device.

Abstract: A signal processing array architecture using a common multiport global memory to interface to a plurality of digital signal processors. The present architecture permits mixing of various types of digital signal processors, commercially available computers, and logic devices. The present signal processing architecture is comprised of a plurality of processing nodes (20) that each comprise a dual processor that is coupled to a local memory by way of a RAM loader bus. An emulated multiport memory is coupled to the dual processor by way of a local bus. A sensor bus is provided for transferring sensor signals from an external sensor to the emulated multiport memory. A global bus is provided that permits communication between each processing node. A bus controller is coupled between the emulated dual port memory and the sensor and global busses for controlling movement of signals to and from the emulated dual port memory.

Abstract: A system for providing distributed control of a resource with centralized configuration management. A network of distributed workstations is provided for controlling a resource such as a large mainframe computer. Server workstations for applying control commands to the resource are attached to each resource, preferably through redundant connections. Remote client consoles are defined which may be connected to the server for control of that resource. Server and resource location and primary and fallback connection paths are maintained by a centralized control server. Upon client console request, the central control server causes the server workstation associated with a particular resource to establish a control session between the server and the client console. A record of each dynamic connection is maintained by the central control server. Upon failure of a client console, the server accesses central server fallback information and establishes a fallback connection with an operational client console.

Abstract: A computer system provides an expanded register set by employing transparent register stacks for each general purpose register. Each general purpose register and its corresponding set of auxiliary registers form a register stack. No register identification bits are required in processor instructions to reference auxiliary registers. A register set select storage area is a programmable register provided for the storage of a value that identifies the currently active register level. The register set select storage area is loaded using two additional processor instructions provided as part of the present invention. A register set switch is used for selecting a data path to the register level specified by the register set select storage area. A PUSHREG instruction is used to push the register stack pointer down one level. A POPREG instruction is used to move the register stack pointer up one register level.

Abstract: A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information.

Abstract: In a microcomputer with a programmable ROM, there is provided an external pin at which a mode select signal is entered so as to select one of three modes, including a MCU mode in which an application system is controlled by an application program which has been stored in the programmable ROM, a PROM mode in which the application program is written into the programmable ROM, and an inline mode in which predetermined data is written to a part of the programmable ROM with the microcomputer mounted on a user system.