Abstract: Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store (MS) and expanded store (ES), or both may be in ES, or both may be in MS. The co-processor controls the asynchronous page movement in parallel with continuing execution of other instructions by the central processor (CP) which requested the page movement. Each page to be moved is specified by an MSB (Move Specification Block). A set of MSBs are addressed by a special type of channel control word (CCW) in a channel program containing one or more CCWs, some of which may address one or more sets of MSBs (one MSB set per CCW) to control the movement of any number of pages. The CPU executes a special ADM SSCH (start subchannel) instruction that passes the page move work to the co-processor to perform the requested page transfer involving one or more sets of MSBs.

Abstract: An interconnection network for interconnection in parallel of a large number (N) of processing elements (PE). The network includes three serial switching stages. The first stage in which the processing elements arc grouped in r clusters of k processing elements each comprising many small fast electronic switches, one for each cluster. The second stage comprises a large number (N) of optical channels, one for each of the N processing elements. The third stage comprises k photodetectors for each of the clusters and electronic switches of the type in the first stage. Each cluster controls k light sources, one for each channel and k photodetectors in the cluster. Interconnection between processing elements in a common cluster are made solely by way of an electronic switch. Interconnection between processing elements in different clusters is made via the optical channels and one or two of the electronic switches.

Abstract: A hardware implementation of a rank order filter includes inputs for inputting a window parameter or window size signal and a target rank signal, thereby permitting programming of the rank order filter to perform rank order filtering within any specified window and relative to any desired target rank.

Abstract: An interface circuit which is connected between a peripheral device and a computer and which can conduct a data transfer at a higher speed. When a first digital data D.sub.1 is output from a peripheral device, the transfer of a memory bus enable request signal DRQ to a computer is halted by transfer control means, and the first digital data is output from the peripheral device in accordance with a false read control signal FIOR from an interface circuit, and held in hold means. When a second digital data is output from the peripheral device, DRQ is transferred to the computer, and 2N-bit data, i.e., N-bit second digital data D.sub.2 output from the peripheral device, and the N-bit first digital data D.sub.1 which is held are simultaneously transferred to the computer in accordance with a read control signal IOR from the computer.

Abstract: A back-end vector parallel computer system suitable for supercomputing in engineering and science, comprising N vector processor units and a cubic array of N.sup.3 memory banks which are shared by N boards and are accessed through row and column common busses wired on all boards in the lattice form from vector processors through anyone of four routing ways in both 2- and 3- dimensional problems, and practicing computation of data accessed through any routing way in parallel for vectors on any section of data array with the selected direction, each vector data being processed by each corresponding vector processor, such parallel computations being usually repeated to the direction successively, and further changing alternatingly the direction of access if necessary for computation to be continued.

Abstract: A rapid reprogramming terminal for reprogramming all electronic warfare and vionics systems aboard an aircraft including the bus controllers for each avionics or electronic warfare bus on the MS-1553 multiplex data bus in the aircraft and the remote terminals connected to each bus in the aircraft. The rapid reprogramming terminal includes a high speed digital signal processor which executes the functions required to reprogram a remote terminal or bus controller through software stored in an electrically erasable program read only memory. The information required to reprogram a remote terminal or bus controller is stored on an IC memory card which is electrically coupled to the digital signal processor.

Abstract: A rapid reprogramming terminal (RRT) adapted for communication with military aircraft MIL-STD-1553 multiplex data bus which includes generally four avionics and one electronic warfare bus on board each aircraft. The RRT may be used to reprogram all electronic warfare and avionics systems aboard and aircraft including the bus controllers for each avionics or electronic warfare bus and the remote terminals connected to each bus. The RRT includes a high speed digital signal processor which executes functions required to reprogram a remote terminal or bus controller through software stored in an electrically erasable programmable read only memory (EEPROM). The information required to reprogram a remote terminal or bus controller is stored on an IC memory card which is electrically coupled to the digital signal processor.