Abstract: A data processing apparatus and corresponding method of data processing are provided. The data processing apparatus comprises a temporary data store configured to store data items retrieved from a memory, wherein the temporary data store selects one of its plural data storage locations in which to store a newly retrieved data item according to a predetermined circular sequence. An index data store is configured to store index items corresponding to the data items stored in the temporary data store, wherein presence of a valid index item in the index data store is indicative of a corresponding data item in the temporary data store. Invalidation control circuitry performs a rolling invalidation process with respect to the index items stored in the index data store, comprising sequentially processing the index items stored in the index data store and selectively marking the index items as invalid according to a predetermined criterion.

Abstract: When a virtual machine writes to a page that is being shared across VMs, a share value is calculated to determine how different the page would be if the write command were implemented. If the share value is below a predefined threshold (meaning that the page would not be “too different”), then the page is not copied (as it would be in a standard copy-on-write operation). Instead, the difference between the contents of the pages is stored as a self-contained delta. The physical to machine memory map is updated to point to the delta, and the delta contains a pointer to the original page. When the VM needs to access the page that was stored as a delta, the delta and the page are then fetched from memory and the page is reconstructed.

Abstract: When a virtual machine writes to a page that is being shared across VMs, a share value is calculated to determine how different the page would be if the write command were implemented. If the share value is below a predefined threshold (meaning that the page would not be “too different”), then the page is not copied (as it would be in a standard copy-on-write operation). Instead, the difference between the contents of the pages is stored as a self-contained delta. The physical to machine memory map is updated to point to the delta, and the delta contains a pointer to the original page. When the VM needs to access the page that was stored as a delta, the delta and the page are then fetched from memory and the page is reconstructed.

Abstract: A storage apparatus performs, in place of a copy process which involves physical resource allocation to a copy destination logical volume, a copy process which allows the copy destination logical volume to refer to an allocation destination managed by a management unit area of a copy source logical volume. A storage unit stores management information relating to the reference destination of the management unit area of the logical volume. A control unit releases the physical resource which has been allocated to the management unit area by exchanging the reference destination of the management unit area specified by a release command from a host computer with the reference destination of the management unit area of the other logical volume corresponding to the specified management unit area.

Abstract: Certain example embodiments provide efficient policy-based access to data stored in memory tiers, including volatile local in-process (L1) cache memory of an application and at least one managed (e.g., non-volatile) in-memory (L2) cache. Operations include receiving an access request for access to a data element in L2; detecting whether a copy of the data element is in L1; if so, copying the data element and the access policy from L2 to L1 and providing the user with access to the copy of data element from L1 if the access policy allows access to the user; and if not, determining, by referring to a copy of the access policy stored in L1, whether the user is allowed to access the data element, and, if the user is allowed to access the data element, providing the user with access to the copy of the data element from the L1 cache memory.

Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract: Sharing local cache from a failover node, including: determining, by a managing compute node, whether a first compute node and a second compute node each have a local cache, where the second compute node is a mirrored copy of the first compute node; responsive to determining that the first compute node and the second compute node each have a local cache, combining, by the managing compute node, local cache on the first compute node and local cache on the second compute node into unified logical cache; receiving, by the managing compute node, a memory access request; and sending, by the managing compute node, the memory access request to an appropriate local cache in the unified logical cache.

Abstract: Sharing local cache from a failover node, including: determining, by a managing compute node, whether a first compute node and a second compute node each have a local cache, where the second compute node is a mirrored copy of the first compute node; responsive to determining that the first compute node and the second compute node each have a local cache, combining, by the managing compute node, local cache on the first compute node and local cache on the second compute node into unified logical cache; receiving, by the managing compute node, a memory access request; and sending, by the managing compute node, the memory access request to an appropriate local cache in the unified logical cache.

Abstract: Technologies for secure inter-virtual-machine shared memory communication include a computing device with hardware virtualization support. A virtual machine monitor (VMM) authenticates a view switch component of a target virtual machine. The VMM adds configures a secure memory view to access a shared memory segment. The shared memory segment may include memory pages of a source virtual machine or the VMM. The view switch component switches to the secure memory view without generating a virtual machine exit event, using the hardware virtualization support. The view switch component may switch to the secure memory view by modifying an extended page table (EPT) pointer. The target virtual machine accesses the shared memory segment via the secure memory view. The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment. Other embodiments are described and claimed.

Abstract: Provided is a technique for improving file load times with dynamic storage usage. A file made up of data blocks is received. A list of storage devices is retrieved. In one or more iterations, the data blocks of the file are written by: updating the list of storage devices by removing any storage devices with insufficient space to store additional data blocks; generating a performance score for each of the storage devices in the updated list of storage devices; determining a portion of the data blocks to be written to each of the storage devices based on the generated performance score for each of the storage devices; writing, in parallel, the determined portion of the data blocks to each of the storage devices; and recording placement information indicating the storage devices to which each determined portion of the data blocks was written.

Abstract: A transactional execution of a set of instructions in a transaction of a program may be initiated to collect memory operand access characteristics of a set of instructions of a transaction during the transactional execution. The memory operand access characteristics may be stored upon a termination of the transactional execution of the set of instructions. The memory operand access characteristics may include an address of an accessed storage location, a count of a number of times the storage location is accessed, a purpose value indicating whether the storage location is accessed for a fetch, store, or update operation, a count of a number of times the storage location is accessed for one or more of a fetch, store, or update operation; a translation mode in which the storage location is accessed; and an addressing mode.

Abstract: Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory. Example technologies may identify a correlation between a subset of the data elements based on correlation criteria. Example technologies may allocate neighboring pages of the flash memory for storing the subset of the data elements. Example technologies may write the subset of the data elements into the allocated pages.

Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Abstract: In one embodiment, a data storage system includes a server system that includes a processor and a local buffer pool configured to store instances for use in catalog requests, and a direct access storage device (DASD) subsystem electrically coupled to the server system and to at least one DASD, where the at least one DASD includes an integrated catalog facility (ICF) configured to provide at least one catalog, and where the data storage system is configured to provide record level sharing (RLS) for the at least one catalog stored to the at least one DASD.

Abstract: A system, method, and computer program product are provided for implementing shared reference counters among a plurality of virtual storage devices. The method includes the steps of allocating a first portion of a real storage device to store data, wherein the first portion is divided into a plurality of blocks of memory and allocating a second portion of the real storage device to store a plurality of reference counters that correspond to the plurality of blocks of memory. The reference counters may be updated by two or more virtual storage devices hosted in one or more nodes to manage the allocation of the blocks of memory in the real storage device.

Abstract: A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.

Abstract: The present disclosure describes systems and techniques relating to accessing data stored in Ternary Content Addressable Memory (TCAM). According to an aspect of the described systems and techniques, a device includes: several blocks of TCAM (Ternary Content Addressable Memory); a hash RAM (Random Access Memory); and processor electronics configured to pre-process control records to (i) identify a subset of bits of the control records, giving priority to bits with no X value, (ii) load the hash RAM based on the identified subset of the bits to be used for hashing of search records to find locations in the several blocks of TCAM, and (iii) order the control records in the several blocks of TCAM in accordance with the identified subset of the bits.

Abstract: A system and a method for managing an expansion read-only memory (ROM), and a management host thereof are provided. The management host is connected with a computer host through a bridge. The management host establishes an address lookup table to assign a virtual function and an expansion ROM corresponding to the virtual function. When a request is issued by the computer host to obtain a size of the expansion ROM, the management host provides data in a shadow register block corresponding to the expansion ROM to the computer host according to the address lookup table. The computer host assigns a memory block in the computer host to the expansion ROM according to the data in the shadow register block. When a request is issued by the computer host to obtain data of the expansion ROM through the bridge, the management host provides the data of the expansion ROM to the computer host according to the memory block.

Abstract: A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue controller. The command queue controller may broadcast the global maintenance command to the clusters including the originating core's cluster. Each of the cores of the clusters may execute the global maintenance command. Each cluster may send an acknowledgement to the command queue controller upon completed execution of the global maintenance command by each core of the cluster. The command queue controller may also send, upon receiving an acknowledgement from each cluster, a final acknowledgement to the originating core's cluster.