Patents Examined by Yong Choe
  • Patent number: 9543025
    Abstract: A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: January 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Fitzpatrick, James M. Higgins, Bernardo Rub, Ryan Jones, Robert W. Ellis, Mark Dancho, Sheunghee Park
  • Patent number: 9524111
    Abstract: A device or system includes a plurality of storage resources each associated with a respective performance class, each being associated with selected performance characteristics such as IOPS, bandwidth, etc. The device or system includes a compute instance having access to allocated storage resources, the allocated storage devices including one or more storage resources. The device or system also includes an optimization component adapted to obtain information relating to utilization by the compute instance component of the allocated storage resources, determine that a change to the allocated storage resources is necessary, based on the information, cause data to be migrated from a first storage resource associated with a first performance class to a second storage resource associated with a second storage class, and cause a removal from the allocated storage resources of the first storage resource and an addition to the allocated storage resources of the second storage resource.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 20, 2016
    Assignee: FittedCloud, Inc.
    Inventors: Prakash Manden, Prashant Parikh, Jin Ren, Jienhua Huang
  • Patent number: 9519432
    Abstract: Performing automated and self-adjusting backup operations by executing the following steps: Determining a time of last backup operation for a data block. Obtaining an audit trail based on the time of last backup operation for the data block and a current time. Ordering read operations and write operations of the data block into a chronological sequence based on the audit trail. Generating a weighting element for read operations and a weighting element for write operations of the data block such that a weighting of read operations are greater than or less than the weighting of a write operations. Calculating a weighted sum of weighted read operations and weighted write operations for said data block. Respond to a result of a comparison between the weighted sum and at least one threshold value by performing a type of backup operation.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Joerg Mueller, Thomas Prause, Michael H. Schlachter
  • Patent number: 9514051
    Abstract: A cache memory is shared by N cores of a processor. The cache memory includes a unified tag part and a sliced data part partitioned into N data slices. Each data slice of the N data slices is physically local to a respective one of the N cores and physically remote from the other N-1 cores. For each core, the cache memory biases allocations caused by the core towards a physically local slice of the core. The cache memory may be arranged as a set-associative cache memory, and allocations may be based on a miss rate of a data slice and a number of M ways allocated to a core. A dispatch queue dispatches requests in a schedule fashion so that only one of the N data slices at a time returns data to each core.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 6, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Bo Zhao, Jiin Lai, Zhongmin Chen
  • Patent number: 9514054
    Abstract: A method and system of persistent cache invalidation ensures cache durability. A storage filter driver of a storage input/output (I/O) stack of a server may be used to capture (i.e., track) write requests made to storage devices prior to the persistent cache becoming operational. Entries in the cache having overlapping address ranges with the tracked write requests may be invalidated before the cache is deemed operational. In this manner, the cache remains consistent with the backing store across the administrative actions or failure event (albeit with less valid entries). Notably, the filter driver tracks (i.e., captures) metadata of the write request (i.e., address range and size of the request) to support invalidation of matching cache entries. As such, the filter driver need not store (record) data associated with the write request.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 6, 2016
    Assignee: NetApp, Inc.
    Inventors: Kenny Speer, Narayan Venkat, David Lively
  • Patent number: 9514057
    Abstract: A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory having a plurality of wordlines and a controller. The controller is configured to use a logical-to-physical address map to convert a logical address to a physical address of a wordline. A plurality of logical addresses in the map point to a single wordline, and the single wordline contains both data associated with the plurality of logical addresses and information about where to find each of the plurality of logical addresses in the single wordline . Storing the information about where to find each of the plurality of logical addresses in the wordline itself avoids the delay and complexity of using a larger logical-to-physical address map or multiple maps.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Alon Marcu, Hadas Oshinsky, Amir Shaharabany, Eran Sharon
  • Patent number: 9514015
    Abstract: A method of distributing data in a distributed storage system includes receiving a file into non-transitory memory and dividing the received file into chunks. The chunks are data-chunks and non-data chunks. The method also includes grouping one or more of the data chunks and one or more of the non-data chunks in a group. One or more chunks of the group is capable of being reconstructed from other chunks of the group. The method also includes distributing the chunks of the group to storage devices of the distributed storage system based on a hierarchy of the distributed storage system. The hierarchy includes maintenance domains having active and inactive states, each storage device associated with a maintenance domain, the chunks of a group are distributed across multiple maintenance domains to maintain the ability to reconstruct chunks of the group when a maintenance domain is in an inactive state.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 6, 2016
    Assignee: Google Inc.
    Inventors: Robert Cypher, Sean Quinlan, Steven Robert Schirripa, Lidor Carmi, Christian Eric Schrock
  • Patent number: 9501233
    Abstract: In general, one aspect of the subject matter described in this specification can be embodied in methods that include receiving, at a computer system, a request to create a snapshot of a virtual storage device, wherein the virtual storage device virtually stores data at virtual addresses, the data being physically stored at a plurality of physical storage locations that are managed by an underlying storage system associated with virtual storage device. The methods can further include identifying, by the computer system, one or more regions of the virtual storage device that have been written to since a previous snapshot of the virtual storage device was created. The methods can additionally include generating a unique identifier for the requested snapshot; and creating the requested snapshot using the identified one more regions and the unique identifier.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 22, 2016
    Assignee: Google Inc.
    Inventors: Matthew S. Harris, Andrew Kadatch, Sergey Khorun, Carl Hamilton
  • Patent number: 9501223
    Abstract: Extended commands are transmitted from computer system via a standard interface to a memory system. The computer system accesses logical memory addresses via an application interface using standard read/write commands which are processed by a memory controller in the memory system. A sequence of read commands for at least two logical memory addresses with address values that differ in at least one bit are output by the computer system. The memory controller compares the sequence of different bits with a predefined bit sequence, the magical address sequence. In the event of a match, a subsequent write command for one of the logical memory addresses is used to open a management connection between the computer system and the memory controller, and the useful data contained in the write command are evaluated by the memory controller and are not written to the addressed memory address.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 22, 2016
    Assignee: Hyperstone GmbH
    Inventors: Martin Roeder, Martin Preiser
  • Patent number: 9495173
    Abstract: The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 15, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Shahar Bar-Or, Eran Sharon, Idan Alrod
  • Patent number: 9495293
    Abstract: A computer implemented method, system, and computer program product for enabling consistency between zones comprising creating a lease agreement between a first zone and at least a second zone; wherein the lease indicates that the first zone is the owner of an object; wherein the lease agreement dictates that a notification is to be sent before a cached object in the first zone is updated if the lease is still valid; wherein the lease indicates the first zone is to send a heartbeat to the second zone within the predetermined period of time if the object has not been changed and the lease is still valid; and setting up heartbeats from the first zone to at least a second zone within a predetermined amount of time; wherein the heartbeat indicates that the lease is still valid and the object has not been changed.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: November 15, 2016
    Assignee: EMC IP Holding Company, LLC
    Inventors: Shashwat Srivastav, Sriram Sankaran, Subba Gaddamadugu, Peter Musial, Andrew Robertson, Huapeng Yuan, Qi Zhang, Jun Luo, Vishrut Shah, Chen Wang
  • Patent number: 9489261
    Abstract: Technology is disclosed for performing background initialization on protection information enabled storage volumes or drives. In some embodiments, a storage controller generates multiple I/O requests for stripe segments of each drive (e.g., disk) of multiple drives of a RAID-based system (e.g., RAID-based disk array). The I/O requests are then sorted for each of the drives according to a pre-determined arrangement and initiated in parallel to the disks while enforcing the pre-determined arrangement. Sorting and issuing the I/O requests in the manner described herein can, for example, reduce drive head movement resulting in faster storage subsystem initialization.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 8, 2016
    Assignee: NETAPP, INC.
    Inventors: Wei Sun, Donald Humlicek, Theresa Segura
  • Patent number: 9483192
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9483205
    Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 1, 2016
    Assignee: Hedvig, Inc.
    Inventors: Avinash Lakshman, Chinmaya Manjunath
  • Patent number: 9483190
    Abstract: A mechanism is provided for improving the average response time of a tape library. Prior to receiving a next access request for data from one of a set of tape mediums, a determination is made as to whether a number of tape drives that are unoccupied is less than a predetermined minimum open tape drive threshold (N). Responsive to the number of tape drives that are unoccupied being less than the predetermined minimum open tape drive threshold (N), a least recently used idle tape medium is unmounted and unloaded from an associated tape drive.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Yuhko Hasegawa
  • Patent number: 9485160
    Abstract: A system and method for optimizing the performance of one or more disks in a storage array in response to access requests by other computer devices and processes across a network. For requests to access to the storage disk from the network, such as a read/write request, a response monitor notes the service time for each access requests by the storage disk, and if the performance in handling the access requests fails to meet, at least, a predetermined time threshold, actions can be taken to migrate data, modify accesses permitted to the disk, or otherwise indicate underperformance.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: November 1, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Marc J. Brooker, Tate Andrew Certain, Roland Paterson-Jones
  • Patent number: 9477599
    Abstract: A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read/write combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events since a store event may not need to reach main memory to complete.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 25, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Blake A. Hechtman, Bradford M. Beckmann
  • Patent number: 9477409
    Abstract: Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajesh M. Sankaran, Murugasamy K. Nachimuthu, Richard P. Mangold
  • Patent number: 9477586
    Abstract: Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventors: Sam Hedinger, Philip Clarke
  • Patent number: 9477421
    Abstract: A method, computer program product, and computing system for defining an initial root slice for a storage system. A first data slice is defined for the storage system. The location of the first data slice of the storage system is identified within the initial root slice. A request for a supplement data slice within the storage system is received. A determination is made as to if the supplement data slice can be added within the storage system without defining a supplemental root slice for a storage system.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 25, 2016
    Assignee: EMC IP Holding Company LLC
    Inventors: Qi Mao, Kamakshi Viswanadha, Ye Zhang, Jean-Pierre Bono, William C. Davenport, Changyong Yu, Alex Zhongbing Yang