Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include receiving a request to create a storage entity on a storage system, the storage entity including data and metadata, the metadata used to manage the storage entity. Upon receiving the request, multiple metadata attributes are identified for the metadata, and for each given identified metadata attribute, a respective metadata region is created on the storage system, and a subset of the metadata having the given metadata attribute is stored to the respective metadata region. Finally, a data region is created on the storage system, and the data is stored to the data region.

Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: A mechanism is provided for multi-tenancy data security. A storage device receives a request for storage from a client device. Responsive to the request for storage being from an existing tenant, the storage device determines whether there is allocated unused storage in a freed space storage pool associated with the existing tenant. Responsive to the allocated unused storage existing in the freed space storage pool, the storage device re-allocates all or a portion of the allocated unused storage existing in the freed space storage pool to an active storage pool associated with the existing tenant in order to satisfy the request such that the client device accesses the allocated unused storage in the active storage pool.

Abstract: Methods and apparatus to provide application access to a flash device having page cache memory and storage class memory via a bus by mapping a user process virtual address space, wherein the process for the application resides on a host having a processor with direct cache-line access to the page cache memory, wherein the user process virtual address space includes at least a partial mapping of physical address windows for one or more separate flash devices.

Abstract: A data cache server may process requests from a data cache client to put, get, and delete data items into or from the data cache server. Each data item may be based on data in a data store. In response to each request to put a data item into the data cache server, the data cache server may determine whether any of the data in the data store on which the data item is based has or may have changed; put the data item into the data cache memory if none of the data in the data store on which the data item is based has been determined to have or maybe to have changed, and not put the data item into the data cache memory if data in the data store on which the data item is based has been determined to have or maybe to have changed.

Abstract: One embodiment provides an eviction system for dynamically-sized caching comprising a non-blocking data structure for maintaining one or more data nodes. Each data node corresponds to a data item in a cache. Each data node comprises information relating to a corresponding data item. The eviction system further comprises an eviction module configured for removing a data node from the data structure, and determining whether the data node is a candidate for eviction based on information included in the data node. If the data node is not a candidate for eviction, the eviction module inserts the data node back into the data structure; otherwise the eviction module evicts the data node and a corresponding data item from the system and the cache, respectively. Data nodes of the data structure circulate through the eviction module until a candidate for eviction is determined.

Abstract: A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract: A storage system, including: (a) a primary storage entity utilized for storing a data-set of the storage system; (b) a secondary storage entity utilized for backing-up the data within the primary storage entity; (c) a flushing management module adapted to identify within the primary storage entity two groups of dirty data blocks, each group is comprised of dirty data blocks which are arranged within the secondary storage entity in a successive sequence, and to further identify within the primary storage entity a further group of backed-up data blocks which are arranged within the secondary storage entity in a successive sequence intermediately in-between the two identified groups of dirty data blocks; and (d) said flushing management module is adapted to combine the group of backed-up data blocks together with the two identified groups of dirty data blocks to form a successive extended flush sequence and to destage it to the secondary storage entity.

Abstract: A storage system may implement dynamic configuration of data volumes. Client utilization of a data volume in a storage system may be tracked or monitored. Based on the utilization of the data volume, configuration recommendations to reconfigure the data volume according to data volume offerings may be determined. The data volume may be configured according to an authorized configuration recommendation. In some embodiments, these recommendations may be provided to a client and selection of the configuration recommendation to perform may be received. In some embodiments, a configuration recommendation may be automatically performed based on previously provided authorization to configure the data volume.

Abstract: A method for accessing a cache memory structure includes dividing a multiple cache elements of a cache memory structure into multiple groups. A serial probing process of the multiple groups is performed. Upon a tag hit resulting from the serial probing process, the probing process for remaining groups exits.

Abstract: A data storage apparatus includes a memory for data storage. The data storage apparatus further includes a data storing section, an access detecting section, and a data deleting section. The data storing section attaches storage-purpose information to data when storing the data in the memory. The storage-purpose information is setting information indicating a purpose for which the image data is stored. The access detecting section attaches access information to the data stored in the memory upon the data being accessed when the data is used. The access information is setting information indicating a purpose for which the image data is used. The data deleting section deletes the data from the memory at a specific timing when the storage-purpose information and the access information attached to the data match.

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Abstract: A multi-queue cache is configured with an initial configuration, where the initial configuration includes one or more queues for storing data items. Each of the one or more queues has an initial size. Thereafter, the multi-queue cache is operated according to a multi-queue cache replacement algorithm. During operation, access patterns for the multi-queue cache are analyzed. Based on the access patterns, an updated configuration for the multi-queue cache is determined. Thereafter, the configuration of the multi-queue cache is modified during operation. The modifying includes adjusting the size of at least one of the one or more queues according to the determined updated configuration for the multi-queue cache.

Abstract: A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set.

Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.

Abstract: A transactional execution of a set of instructions in a transaction of a program may be initiated to collect memory operand access characteristics of a set of instructions of a transaction during the transactional execution. The memory operand access characteristics may be stored upon a termination of the transactional execution of the set of instructions. The memory operand access characteristics may include an address of an accessed storage location, a count of a number of times the storage location is accessed, a purpose value indicating whether the storage location is accessed for a fetch, store, or update operation, a count of a number of times the storage location is accessed for one or more of a fetch, store, or update operation; a translation mode in which the storage location is accessed; and an addressing mode.

Abstract: Various embodiments for managing data objects stored in a tiered data object storage environment, by a processor device, are provided. In one embodiment, a method comprises measuring a service level of a data set tagged to be collocated, and comparing accumulated service levels for a data distribution of the data set to a predetermined service level threshold value, such that if the predetermined service level threshold value is reached, a collocated data optimization event is performed.

Abstract: Methods and systems for the optimization of available computing resources within a virtual environment are disclosed. An exemplary method comprises determining the sizes of the computing resources available to the virtual machine and determining optimal data structures for the virtual machine based on the sizes of the computing resources. The optimal data structures may include an indexing data structure and a historic data. The method may further comprise allocating a Random Access Memory (RAM) and disk storage to the optimal data structures and configuring the optimal data structures within the RAM and the disk storage. The optimization of data structures involves balancing requirements of the indexing data structure and the historic data.

Abstract: An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.