Abstract: An initialization geo-locking system includes a chassis housing a location determination subsystem and an initialization management subsystem. During an initialization process that begins in response to receiving initialization power, the initialization management system determines that geo-locking is activated and, in response, causes power to be provided to the location determination subsystem and then subsequently identifies a first current location determined by the location determination subsystem. The initialization management subsystem then determines whether the first current location determined by the location determination subsystem corresponds to an authorized initialization location stored in the initialization management subsystem and, if so, halts the initialization process while, if not, allows the initialization process to complete.

Abstract: A deployment system for IoT including an edge server, multiple gateways, and multiple agent modules is disclosed. Each gateway is respectively connected with different peripheral devices to support different function. The edge server includes a flow editor used to edit a flow for a target gateway. The edge server performs a deploying procedure to the target gateway in accordance with the flow, wherein the deploying procedure is to first read a script and a parameter of one or more function nodes included in the flow, then encapsulate the script and the parameter into a packet, and then transmit the packet to the target gateway through one of the agent modules. The target gateway receives the packet through one of the agent modules and sequentially executes the function nodes according to the content of the flow, so as to implement a corresponding IoT function.

Abstract: A vehicle control apparatus may include a host including a driving application of a vehicle controller and a hardware security module that determines whether to transmit a message for allowing booting of the host to the host, according to a result of a secure boot at an n-th cycle, and determines whether to perform the secure boot at a (n+1)-th cycle, depending on whether the message is transmitted to the host.

Abstract: A method is disclosed for maintaining a current operating state of an enclosure when a controller card of the enclosure is repaired and/or replaced. In one embodiment, such a method maintains, within a controller card of an enclosure, operating parameters used to establish an operating state of the enclosure. The method further offloads, from the controller card while the controller card is installed in the enclosure, the operating parameters to a location external to the controller card. Upon removal of the controller card from the enclosure, the method maintains the operating state of the enclosure using the operating parameters stored in the external location. Upon reinstalling the controller card in the enclosure, the method optionally retrieves the operating parameters from the external location and initializes the controller card with the operating parameters. A corresponding system and computer program product are also disclosed.

Abstract: Example implementations includes a method of partitioning a non-transitory memory device by detecting a boot state of a processing device including a non-transitory memory device, identifying a startup state of the processing device based on the boot state, and partitioning the memory device into at least one secure address region, in accordance with a determination that the startup state satisfies an operating state condition. Example implementations also include a method of generating a secure partition associated with a non-transitory memory device by identifying a target processing instruction restricted to execution at a secure subsystem of a processing device, assigning to the target processing instruction a secure address, associating the secure address with a secure address region of a non-transitory memory device of the processing device, and generating a secure partition table including the secure address.

Abstract: A computing device of a database system includes a plurality of processing modules, a computing device operating system, and an application specific operating system. The application specific operating system includes at least one custom instruction set that configures operation of a configurable set of processing modules of the plurality of processing modules based on generating, for each processing module of the configurable set of processing modules, a corresponding configuration signal indicating a selected instruction set of either the computing device operating system or the application specific operating system. Each processing module of the configurable set of processing modules operates in accordance with the selected instruction set based on the corresponding configuration signal.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: Techniques are disclosed for deploying a computing resource (e.g., a service) in response to user input. A computer-implemented method can include operations of receiving (e.g., by a gateway computer of a cloud-computing environment) a request comprising an identifier for a computing component of the cloud-computing environment. The computing device receiving the request may determine whether the identifier exists in a routing table that is accessible to the computing device. If so, the request may be forwarded to the computing component. If not, the device may transmit an error code (e.g., to the user device that initiated the request) indicating the computing component is unavailable and a bootstrap request to a deployment orchestrator that is configured to deploy the requested computing component. Once deployed, the computing component may be added to a routing table such that subsequent requests can be properly routed to and processed by the computing component.

Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

Abstract: A power management system and method for an SRAM circuit and an FPGA chip are provided. The power management system includes a power management, a power management controller and an oscillator. The power management circuit include a power-on reset circuit used to determine whether powering-on of a core voltage and an analog input-output voltage of power supply voltages of the power management circuit is completed. The power management controller and the oscillator are used to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed, and further used to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on. Powering-on sequences of various internal power supplies of the FPGA chip are clear, and power consumption of the FPGA chip can be reduced.

Abstract: The present disclosure describes automated generation of early warning predictive insights derived from contextual analysis of user activity data of a distributed software platform. Predictive insights are automatically generated from analysis of user activity through implementation of trained artificial intelligence (AI) modeling. User activity data is accessed pertaining to user interactions by a plurality of users a software data platform. The trained AI modeling generates a plurality of mobility determinations that identify changes in patterns of user behavior over a current temporal filter associated with the user activity data. The plurality of mobility determinations is curated using business logic rules that evaluate a relevance of the mobility determinations. One or more predictive insights may be generated and presented via a graphical user interface notification.

Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

Abstract: During a boot process of a computing device, a boot loader loads a kernel and an initial RAM disk image from a persistent storage device into RAM. The initial RAM disk image includes a file system that includes a camera application. The kernel is invoked, and the kernel mounts a RAM disk from the initial RAM disk image as a root file system. The kernel causes an initiation of the camera application into a user space. The camera application obtains an image frame from a camera. The camera application processes the image frame to generate a processed image frame, and provides the processed image frame to a frame buffer for presentation of the processed image frame on a display device.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: In one embodiment, a gaming system, method, and device may have a memory having a plurality of power management rules and a processor configured to receive a power status information from another device, retrieve at least one power management rule from the memory, and configure a power state of the gaming device or its peripheral device based on the power status information and the at least one power management rule.

Abstract: A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.

Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.

Abstract: An information handling system may include a physical storage resource having a portion thereof that includes files that are usable during boot of the information handling system; at least one processor; and a Basic Input/Output System (BIOS) including instructions that are executable by the at least one processor for: during a boot process, determining whether any of a plurality of BIOS events have taken place during a previous boot process, wherein the plurality of BIOS events are indicative of malicious behavior during the previous boot process; and in response to a determination that at least a predetermined number of the plurality of BIOS events have taken place during the previous boot process, carrying out a remedial action during the boot process.

Abstract: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not affect the system beyond the quantizer.