Abstract: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not effect the system beyond the quantizer.

Abstract: An information processing device includes a first information processing part having a first calculation part and a second information processing part having a second calculation part, which are communicated with each other. The first information processing part includes a first communication part and a first data storage part. The first calculation part is configured to execute a first communication device driver, a first periodic communication application, a first non-periodic communication application, and a first data processing application. The first data processing application integrates data which are read from a transmission periodic data list stored in the first data storage part with data which are read from a transmission non-periodic data list stored in the first data storage part to process into transmission integrated data, and the transmission integrated data are transmitted from the first communication part through execution of the first communication device driver.

Abstract: A method for creating devices facilitating secure data transmission, storage and key management. At least two devices are each comprised of at least part of a physically unclonable function unit originally shared by the at least two devices on a single, monolithic original integrated circuit. The process includes physically segmenting the shared physically unclonable function unit between the at least two devices. The at least two devices which share the single, monolithic integrated circuit are physically separated into individual device units.

Abstract: A system, method and apparatus to authenticate an endpoint having a secure memory device. For example, at boot time of the endpoint, a cryptographic hash value of the boot loader stored in the memory device is used to generate a device identifier of the memory device; and identification data of multiple components of the endpoint is used with the device identifier of the memory device to generate a first key pair key and a second key. A counter value is retrieved from a monotonic counter to generate a certificate signed using a private key in the first key pair. The certificate can be sent over the computer network to a remote server for authentication using a public key in the first key pair. The second key pair can be authenticated and used to establish encryption for a communication connection between the endpoint and the server.

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

Abstract: Disclosed is an electronic device comprising: a connection circuit configured to provide an electrical connection of an external power supply device; a processor electrically connected to the connection circuit; a memory operatively connected to the processor; and a reset circuit electrically connected to the connection circuit and operatively connected to the processor. The processor is configured to” transmit, to the reset circuit, an interrupt signal during a first time at least partially based on the identification of the connecting to the external power supply device through the connection circuit, and the reset circuit may be configured to: determine whether the interrupt signal is received within a second time after the connecting to the external power supply device through the connection circuit, and transmit, to the processor, a reset signal for a hardware reset of the processor based on the interrupt signal not being received within the second time.

Abstract: A vehicular device includes a CPU. The CPU is set in a rated state in which the CPU operates at a rated operating clock and a high speed state in which the CPU operates at an operating clock higher than the rated operating clock. The high speed state is changeable in the operating clock and the rated state is not changeable in the rated operating clock.

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

Abstract: Methods and apparatus to manage power and performance of computing devices based on user presence are disclosed. An apparatus includes an engagement detector to determine an engagement of a user with a device based on at least one of image data generated by an image sensor or an application running on the device; and an operation mode selector to select one of a plurality of operation modes for the device based on a level of engagement of the user, the plurality of operation modes including (1) a first operation mode associated with the device operating at a first performance level and a first power level and (2) a second operation mode associated with the device operating at a second performance level and a second power level, the first performance level being higher than the second performance level, the first power level being higher than the second power level.

Abstract: A secure Basic Input/Output System (BIOS)-enabled passthrough system includes a computing device having a computing device component, and a BIOS subsystem in the computing device that is coupled to the computing device component. The BIOS subsystem enables primary access to the computing device component to BIOS drivers. The BIOS subsystem may receive a secondary access session start request from a first BIOS driver to start a secondary access session to use secondary access to the computing device component, it retrieves a first BIOS driver identifier for the first BIOS driver based on the secondary access session start request, determines that the first BIOS driver identifier is a secondary-access-authorized BIOS driver identifier and, in response, begins the first secondary access session and may performs secondary access operation(s) on the computing device component in response to receiving secondary access command(s) from the first BIOS driver during the secondary access session.

Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: In general, embodiments of the invention relate to implementing a secure boot process in information handling systems that supports both an external root of trust (eRoT) and an internal root of trust (RoT). Further, embodiments of the invention relate to binding a management controller to a specific chassis and, in the case where the eRoT is used, to an eRoT. When the management controller and the chassis are provisioned according to one or more embodiments of the invention, security checks may be performed by management controller executing an initial program loader (IPL) using the aforementioned bindings. If the bindings are not present or do not match, then the boot process halts and the user is unable to use the information handling system.

Abstract: The architecture includes four largely independent subsystems which are arranged hierarchically and each form an isolated Fault-Containment Unit (FCU). At the top of the hierarchy is a secure subsystem, the Fault-Tolerant Decision Subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are insecure because they contain complex software executed on non-fault-tolerant hardware. Experience has shown that it is difficult to find all design errors in a complex software system and to prevent an intrusion. The redundancy and diversity inherent in this architecture masks every error—even a Byzantine error—of an insecure subsystem in such a way that no safety-critical failure can occur.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: During a power-on self-test (POST), a basic input/output system (BIOS) retrieves an attribute value associated with the persistent memory device, and compares the attribute value to a default value. In response to the attribute value matching the default value, the BIOS may determine that a firmware management protocol was not executed during a previous POST. In response to the attribute value not matching the default value, the BIOS may compare the attribute value to a current firmware version of firmware within the persistent memory device.

Abstract: An operating method of a power optimization scheduler is provided, where the operating method of a power optimization scheduler includes obtaining information regarding a neural network (NN) model, determining a voltage value for a task to be performed by at least one processing device, based on the obtained information regarding the NN model, and controlling a power management device to apply a voltage corresponding to the determined voltage value to the at least one processing device.

Abstract: A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.

Abstract: A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.