Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for monitoring a parameter of one or more of the hardware devices of the IHS when a custom BMC firmware stack is executed on the BMC. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. When the parameter exceeds a specified threshold, the instructions are further executed to control the BMC to perform one or more operations to remediate the excessive parameter.

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

Abstract: The invention is part of the field of computer technology. It describes the architecture of a secure automation system and a method for safe autonomous operation of a technical apparatus, in particular a motor vehicle. The architecture disclosed herein solves the problem that any Byzantine error in one of the complex subsystems of a distributed real-time computer system, regardless of whether the error was triggered by a random hardware failure, a design error in the software or an intrusion, must be recognized and controlled in such a way that no security-relevant incident occurs. The architecture includes four largely independent subsystems which are arranged hierarchically and each form an isolated Fault-Containment Unit (FCU). At the top of the hierarchy is a secure subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are insecure because they contain complex software executed on non-fault-tolerant hardware.

Abstract: There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

Abstract: A controller and techniques for expanding its feature capabilities. Techniques may incorporate using an external memory to store feature sets that can be downloaded to an internal memory for intimate incorporation and usage by the controller. The external memory may be large in comparison to the internal memory. External storage of additional feature sets allows for use of a small and simple controller with access to numerous feature sets that otherwise could not be incorporated by the small controller.

Abstract: Scalable life-cycle maintenance of hardware. In an embodiment, a software-defined Preboot eXecution Environment (PXE) server is executed to receive a request, comprising an identifier, from hardware. The identifier is compared to a plurality of attribute sets. When the identifier does not match any of the attribute sets, a task graph is generated for a PXE process for the hardware, and an initial stage of the task graph is initiated. Otherwise, when the identifier matches one of the attribute sets, the task graph associated with that attribute set is retrieved, and the next stage in the task graph is initiated. In addition, a display key may be used to tether hardware with a user system. Furthermore, hardware may be validated by comparing signatures using a validating operating system, and a boot order of operating systems in the hardware may be changed once the hardware device is validated.

Abstract: Examples associated with service kiosk device configuration are described. One example includes authenticating a user at a service kiosk. The user is authenticated based on a credential provided by the user. A service profile associated with the user is loaded. The service profile describes a device assigned to the user. An operable connection between the service kiosk and the device is established. Service information is obtained from the user via an interface at the service kiosk, from the service profile, and from the device via the operable connection. The service information describes a technical issue associated with the device. The device is configured via the operable connection to resolve the technical issue.

Abstract: The present invention provides a smart overclocking method for a computer device with a multi-core CPU and abasic input/output system (BIOS) where an overclocking database is stored therein, which comprises: booting the computer device, logging in the BIOS and performing an overclocking function; acquiring overclocking parameters from the overclocking database; conducting adjustment/settlement of the clock rate and the voltage of the multi-core CPU based on the overclocking parameters; conducting a Heavy Load Testing (HLT) on the multi-core CPU; reading out working results data of the multi-core CPU and determining whether any of them have exceeded limits. Hence, overclocking can be completed within 10 min. or less, without causing shut down of the computer device, and without causing working temperature or working voltage of multi-core CPU to be higher than 90° C. or 1500 mV during Heavy Load Testing (HLT).

Abstract: In an embodiment, a powered device (PD) interface circuit includes a lower priority PD and a higher priority PD. The lower priority PD is configured to receive, and to couple to a power supply onboard a subsystem, a first power signal from first power source equipment (PSE). And the higher priority PD is configured to receive a second power signal from second PSE, to couple the second power signal to the power supply, and to prevent the lower priority PD from coupling the first power signal to the power supply while the higher priority PD is coupling the second power signal to the power supply. That is, such a PD interface circuit is configured to impart a respective priority to each PD such that if two or more PDs receive power from respective PSEs, then the interface circuit enables only the PD having the higher priority to couple a corresponding PSE power signal to the power supply onboard the subsystem.

Abstract: A computing device comprises a plurality of nodes and a plurality of operating system layers. The plurality of operating system layers includes a local database operating system and a sub-system database operating system. The plurality of nodes utilize the local database operating system to execute at least one database operation independently of other ones of the plurality of nodes. The computing device utilizes the sub-system database operating system in conjunction with other ones of a plurality of computing devices of at least one sub-system to facilitate execution of at least one sub-system operation of the at least one sub-system.

Abstract: A secure boot policy may be stored in the information handling system and used to create a trusted relationship with a CPU, including a neutral CPU that has not been fused with an OEM key. The secure boot policy may be a data blob including platform-specific identification information (e.g., one or more of flash memory unique ID, motherboard ePPID), a boot policy (e.g., specifying to enable or disable neutral CPU fusing), and a signature. The secure boot policy may be stored in a one-time-programmable (OTP) storage of the information handling system, such as an OTP region in the serial peripheral interface (SPI) flash memory part storing the basic input/output system (BIOS). The BIOS may verify the secure boot policy using a public key and check if the boot policy is bound to current BIOS flash part and/or system configuration, and then apply the boot policy if the verification is passed.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

Abstract: In accordance with an embodiment, a method and system are provided to create and analyze grouped events. The method and system involve obtaining, at a network node, event data of measured real events detected at one or more locations of a monitored system according to a first criterion. The event data for each real event defines one or more parameters/dimensions of the real event. The method and system further involve aggregating the detected real events into groups according to at least one or more parameters/dimensions of the detected real events, and analyzing one or more of the aggregated groups of detected events to identify conditions on the monitored system or take action when a condition is identified from the one or more aggregated groups of tracked events. The tracked real events may include an alarm event as well as a system event.

Abstract: An article of manufacture, a machine, process for using the articles and machines, processes for making the articles and machines, and products produced by the process of making, along with necessary intermediates, directed to assessing the energy consumption of networks, typically computer networks, and/or applications of assessments made thereby. Industrial applicability is representatively directed to energy consumption/conservation and efficiency, such as in networks, along with control and implementation therefrom, as well as in networking, control systems communications and related systems, receiver systems, and components used in assessing and carrying out the same.

Abstract: An automotive control module includes a microcontroller having an access port, and that permits reprogramming of its functions responsive to a voltage at the access port being greater than a first predefined threshold upon power-up or reset thereof. The automotive control module also includes a boot assist control circuit lacking logical elements and including a pair of input ports, an output port directly electrically connected to the access port, and a plurality of capacitors, resistors, and transistors electrically connected between the pair and output port. The plurality outputs a voltage to the output port at least equal to the first predefined threshold responsive to voltages at both the input ports being greater than a second predefined threshold, and outputs a voltage to the output port less than the first predefined threshold responsive to the voltage at either one of the input ports being less than the second predefined threshold.

Abstract: A data storage device restoring method is provided, which is adapted to a data storage device. The data storage device includes an SSD controller, a power management circuit, a non-volatile memory, and a reset circuit. The data storage device restoring method includes: the power management circuit determines whether a normal signal from the SSD controller is received within a predetermined time; if not, the power management circuit resupplies power to the data storage device but stops supplying power to the non-volatile memory, thereby the SSD controller stays in a read-only memory mode to automatically execute the data storage device restoring process.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for rollback resistant security are disclosed. In one aspect, a method, during a boot process of a computing device, includes the actions of obtaining a secret key derived from device-specific information for the computing device. The method further includes verifying that a signature for a software module is valid. The method further includes obtaining information indicating a current version of the software module. The method further includes using the secret key to generate a first encryption key corresponding to the current version of the software module and a second encryption key corresponding to a prior version of the software module. The method further includes preventing future access to the secret key until the computing device is rebooted. The method further includes providing the software module access to the first encryption key and the second encryption key.