Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: An example method includes detecting an event in an electronic system. The electronic system includes an electronic component and a switched mode power supply. The electronic component draws an amount of power from the switched mode power supply during operation. In response to detecting the event, the electronic component is operated to cause the electronic component to change the amount of power that the electronic component draws from the switched mode power supply. The change in the amount of power that the electronic component draws causes the switched mode power supply to output a signal that is evidence of the event.

Abstract: An objective is to provide an information processing device that can be started up stably, and an information processing method. A configuration execution unit of an information processing device writes configuration data into an FPGA. A clock signal monitoring unit detects whether a clock signal supplied from a CPU to the FPGA is stable or not, on condition that a configuration is complete. A startup processing unit starts up the CPU and the FPGA on condition that the clock signal is stable.

Abstract: Methods and electronic devices are provided. Account access information is received, at an electronic device, from an external electronic device. The account access information is transmitted to a server. Account-related information about the external electronic device is received from the server. An account of the external electronic device is logged into based on the account-related information. A configuration of the electronic device is changed while logged into the account of the external electronic device.

Abstract: A telematics device coupled to an input/output expander is provided. The telematics device includes a controller, an input/output expander interface for coupling the telematics device to the controller and a memory. The memory has machine-executable programming instructions which configure the telematics device to power-cycle the input/output expander interface by a plurality of power cycles having progressively increasing power-off durations, in response to detecting a power fault condition on the input/output expander interface.

Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: A system includes a first cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals synchronized with each other, a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals to a plurality of blades. Each blade includes a plurality of programmable logic devices, an operation of which is synchronized based on the first plurality of clock inputs. Each blade includes a second cross-point switch to receive a blade signal of the plurality of blade signals. The second cross-point switch outputs a second plurality of clock outputs based on the received blade signal, and the second plurality of clock outputs are provided to the programmable logic devices.

Abstract: A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code, and does not expose un-encrypted data, including the executable code, on an external memory interface, including a DRAM interface. Further, only the specific processing chip that was used to initially write the encrypted executable code to the external non-volatile memory chip is able to decrypt the encrypted executable code. The decryption uses a key unique to the processing chip and created at manufacturing time that is never CPU-accessible, forming a secure hardware association between the two chips.

Abstract: A module may have more than one device, such as an IoT device, that requires bootstrapping. A first device may be provisioned with a pre-shared key (PSK). The first device, such as an IoT device, may bootstrap in a conventional manner using its PSK. A second device without a PSK may be added to the module post-manufacture. The first device may share registration details with the second device and also with an LwM2M server. When contacted by the second device, the LwM2M server may associate the second device with the first device and treat them as one from an operational standpoint, reducing the need for pre-shared keys across domains lacking an existing trust relationship.

Abstract: An industrial internet of things gateway boot method is described wherein installation, operation and maintenance phases are controlled to limit the chance of a malicious attack on a connected network.

Abstract: A method may include, in an operating system, implementing a sensor hub in firmware of a platform controller hub of an information handling system, the sensor hub configured to implement a plurality of sensor physical microdrivers, each of the plurality of sensor physical microdrivers corresponding to a respective sensor of a plurality of sensors and configured to communicate a signal representing a physical quantity sensed by the respective sensor; a plurality of algorithm microdrivers implemented as virtual microdrivers, each of the plurality of algorithm microdrivers corresponding to a respective sensor physical microdriver of the plurality of sensor physical microdrivers; and a user-awareness arbitration microdriver implemented as a virtual microdriver and configured to receive an arbitration policy for user awareness detection, receive sensor information from the plurality of algorithm microdrivers, and based on the arbitration policy, apply arbitration logic to the sensor information to determine a user

Abstract: The present disclosure describes methods, devices, and storage mediums for adjusting computing resource. The method includes obtaining an expected pooling time of a target pooling layer and a to-be-processed data volume of the target pooling layer; obtaining a current clock frequency corresponding to at least one computing resource unit used for pooling; determining a target clock frequency according to the expected pooling time of the target pooling layer and the to-be-processed data volume of the target pooling layer; and in response to that the convolution layer associated with the target pooling layer completes convolution and the current clock frequency is different from the target clock frequency, switching the current clock frequency of the at least one computing resource unit to the target clock frequency, and performing pooling in the target pooling layer based on the at least one computing resource unit having the target clock frequency.

Abstract: Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.

Abstract: The present invention relates to a securing boot controller for an embedded system, the embedded system further comprising an operational module incorporating an operational function of the system, and a verification module incorporating a function of verifying various components of the system; The controller is configured to: upon cold startup of the system, make the verification function executable at boot up to perform a functional verification including a verification of the authenticity and integrity of the operational function; upon successful completion of the functional verification, at each warm start following said cold start of the system, making the operational function executable at boot up.

Abstract: An information handling system may include at least one processor; and a computer-readable medium having instructions thereon that are executable by the at least one processor for: prior to initialization of an operating system, executing a pre-boot environment; and within the pre-boot environment, downloading a universal filesystem driver from a first back-end server and loading the universal filesystem driver in the pre-boot environment, wherein the universal filesystem driver is a single pre-boot firmware volume that comprises drivers for a plurality of different filesystems.

Abstract: A system and method for energy conservation in a virtual universe, the method comprising: determining, at a server, available energy conservation options associated with an avatar of the virtual universe; determining, at the server, selected energy conservation options of the available energy conservation options; and applying, at the server, the selected energy conservation options to portions of the virtual universe associated with the avatar.

Abstract: A power-availability-based power delivery configuration system includes a power scaling system that is coupled to a device and a power system. The power scaling system includes an adjustable power scaling circuit that is configured to convert power received from the power system from a first power level to a second power level. A power scaling controller is coupled to the device, the power system, and the power scaling circuit. The power scaling controller identifies a power amount available from the power system and, based on the power amount available from the power system, determines power delivery settings for the adjustable power scaling circuit and configures the adjustable power scaling circuit using the power delivery settings. The power scaling controller may also determine device settings for the device based on the power amount available from the power system and configure the device using the device settings.

Abstract: A method for handling input/output (I/O) expansion power faults in a telematics device is provided. The method includes setting an I/O expander power-off duration to an initial value and powering on an I/O expander interface. In response to detecting a power fault at the I/O expander interface, the I/O expander interface is powered-off dur the power-off duration and the power-off duration is increased. If the power-off duration is greater than the power-off duration limit, the I/O expander interface is permanently powered-off. The steps are repeated until either the power fault does not recur, or the I/O expander interface is permanently powered-off.