Abstract: Apparatus and methods are disclosed. In one example, a semiconductor package includes a first die that has a first surface and a first electrical lead at or near the first surface. The semiconductor package also includes a substrate that has a second surface and is coupled to the first die at a first interface. The substrate also includes a first electrode at or near the second surface and at least a first portion of an integrated passive device that is coupled to the first electrode. The first electrode is aligned with and coupled to the first electrical lead across the first interface.

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

Abstract: A microelectronics package comprising a package core and an inductor over the package core. The inductor comprises a dielectric over the package core. The dielectric comprises a curved surface opposite the package core. At least one conductive trace is adjacent to the package core. The at least one conductive trace is at least partially embedded within the dielectric and extends over the package core. A magnetic core cladding is over the dielectric layer and at least partially surrounding the conductive trace.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

Abstract: An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

Abstract: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.