Patents by Inventor Adel A. Elsherbini
Adel A. Elsherbini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220199546Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Gerald S. Pasdast, Kimin Jun, Zhiguo Qian, Johanna M. Swan, Aleksandar Aleksov, Shawna M. Liff, Mohammad Enamul Kabir, Feras Eid, Kevin P. O'Brien, Han Wui Then
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Publication number: 20220199450Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Michael J. Baker, Aleksandar Aleksov, Feras Eid
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Patent number: 11367707Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.Type: GrantFiled: September 26, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Gerald S. Pasdast
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Patent number: 11367689Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: December 21, 2020Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Publication number: 20220192042Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Mohammad Enamul Kabir, Adel A. Elsherbini, Manish Chandhok
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Publication number: 20220189861Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Aleksandar Aleksov, Mohammad Enamul Kabir, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid
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Publication number: 20220189839Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Shawna M. Liff, Aleksandar Aleksov
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Publication number: 20220189850Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Applicant: Intel CorporationInventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Xavier Francois Brun, Aleksandar Aleksov, Feras Eid
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Publication number: 20220181276Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
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Publication number: 20220173489Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Applicant: Intel CorporationInventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
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Patent number: 11348897Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.Type: GrantFiled: December 29, 2017Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
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Patent number: 11348895Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 18, 2020Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11348882Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.Type: GrantFiled: November 13, 2019Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Veronica Aleman Strong
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Patent number: 11348912Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 21, 2020Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11342320Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 29, 2017Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11342305Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: December 29, 2017Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Lift, Johanna M. Swan
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Patent number: 11342243Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat transfer fluid conduit extending through the substrate. In one embodiment, the heat transfer fluid conduit may be lined with a metallization within the substrate. In a further embodiment, the heat transfer fluid conduit may comprise multiple fluid channels for the removal of heat from multiple surfaces of the at least one integrated circuit device. In still a further embodiment, the substrate may include a molded layer, wherein at least one fluid channel is formed in the molded layer.Type: GrantFiled: September 25, 2018Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Johanna Swan
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Patent number: 11335663Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 29, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11335665Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 29, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11335642Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: GrantFiled: December 29, 2017Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan