Patents by Inventor Akihiro Kikuchi

Akihiro Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117483
    Abstract: The problem addressed by the present invention is to provide a copper-coated aluminum wire material with a reduced weight and excellent adhesiveness, and a production method therefor. This copper-coated aluminum wire material is provided with an aluminum wire material comprising aluminum or an aluminum alloy and a thin copper film covering the aluminum wire material. The space factor of the thin copper film is in the range of 0.2% to 4% and the adhesiveness between the aluminum wire material and the thin copper film based on a scratch test compliant with JIS R 3255 is at least 10 mN.
    Type: Application
    Filed: February 28, 2022
    Publication date: April 11, 2024
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Akihiro KIKUCHI, Hitoshi KITAGUCHI, Yasuo IIJIMA, Kazuto HIRATA
  • Patent number: 11953843
    Abstract: A powder container includes a powder chamber for containing powder for forming images, a powder outlet formed in a face of the powder container, and a shutter assembly to open and close the powder outlet and including first and second shutters. The first shutter is movable between a sealing position to close the powder outlet and an open position to open the powder outlet and includes a pressed member to cancel retention of the first shutter at the sealing position. The second shutter includes a pressing projection that interferes with the pressed member of the first shutter and is movable between a shielding position to cover the pressed member without interference between the pressing projection and the pressed member and a releasing position to press the pressed member with the pressing projection.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 9, 2024
    Assignee: RICOH COMPANY, LTD.
    Inventors: Kentaro Nodera, Emi Kita, Akihiro Takayama, Susumu Tateyama, Shinnosuke Koshizuka, Tatsuya Kubo, Teppei Kikuchi
  • Patent number: 11605869
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: March 14, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Akihiro Kikuchi, Genro Kato, Kosuke Nishino, Nobuo Ikemoto
  • Patent number: 11411428
    Abstract: In a power converter including: a first DC-DC converter, an inverter, and a control circuit, a second DC-DC converter that controls an input and an output of a power storage unit is connectable to a DC bus. The control circuit deactivates a reverse power flow suppression function for suppressing a reverse power flow from the inverter to a power system when the second DC-DC converter is not connected to the DC bus and activates the reverse power flow suppression function when the second DC-DC converter is connected to the DC bus.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 9, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kota Maeba, Akihiro Kikuchi, Wataru Horio, Hiroyuki Fujii, Kenji Hanamura, Tomoki Ito
  • Patent number: 11025056
    Abstract: In a power converter, a DC bus is supplied with a DC power from a voltage conversion circuit for regulating a voltage of a power output from a DC power supply, a voltage of the DC power being regulated by the voltage conversion circuit. An inverter converts a DC power on the DC bus into an AC power and supplies the AC power as converted to a power system. A controller controls the inverter. When it is necessary to suppress an output, the controller suppresses the AC power supplied by the inverter to increase a voltage on the DC bus.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 1, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akihiro Kikuchi, Kenji Hanamura, Tomoki Ito
  • Publication number: 20210151845
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 20, 2021
    Inventors: Takahiro BABA, Akihiro KIKUCHI, Genro KATO, Kosuke NISHINO, Nobuo IKEMOTO
  • Patent number: 10990313
    Abstract: In a multi-storage node system including a plurality of storage nodes, a plurality of storage nodes include a plurality of drives that store data and a control unit that controls writing of data to the drives. The control unit divides storage areas of the plurality of drives into a plurality of physical chunks, allocates the divided physical chunks to logical chunks, and stores data. A plurality of storage nodes are divided into fault sets affected by a single failure and manage the multi-storage node system. The control unit of one primary node that manages the multi-storage node system among a plurality of storage nodes includes a database for managing allocation of the physical chunks of a plurality of storage nodes to the logical chunks for each drive, each storage node, or for each fault set.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Akihiro Kikuchi, Takayuki Fukatani
  • Publication number: 20210088552
    Abstract: The present invention focuses on a material constituting a contact pin and a processing technique of the material, and is directed to manufacturing a conductive member by using a material and a processing technique which are different from those in the related art. The conductive member is obtained by applying etching treatment to a copper-silver alloy including copper and silver while using at least copper alloy etching liquid, but silver etching liquid may also be selectively added to the copper alloy etching liquid.
    Type: Application
    Filed: July 9, 2018
    Publication date: March 25, 2021
    Applicants: Kyosei Co., Ltd., National Institute of Materials Science
    Inventors: Tsutomu SATO, Yoshikazu SAKAI, Akihiro KIKUCHI
  • Patent number: 10944145
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: March 9, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Akihiro Kikuchi, Genro Kato, Kosuke Nishino, Nobuo Ikemoto
  • Publication number: 20200264794
    Abstract: In a multi-storage node system including a plurality of storage nodes, a plurality of storage nodes include a plurality of drives that store data and a control unit that controls writing of data to the drives. The control unit divides storage areas of the plurality of drives into a plurality of physical chunks, allocates the divided physical chunks to logical chunks, and stores data. A plurality of storage nodes are divided into fault sets affected by a single failure and manage the multi-storage node system. The control unit of one primary node that manages the multi-storage node system among a plurality of storage nodes includes a database for managing allocation of the physical chunks of a plurality of storage nodes to the logical chunks for each drive, each storage node, or for each fault set.
    Type: Application
    Filed: September 6, 2019
    Publication date: August 20, 2020
    Inventors: Akihiro KIKUCHI, Takayuki FUKATANI
  • Publication number: 20200227806
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Takahiro BABA, Akihiro KIKUCHI, Genro KATO, Kosuke NISHINO, Nobuo IKEMOTO
  • Patent number: 10658188
    Abstract: Provided is a method of manufacturing a semiconductor device with which a trench shape having vertical, flat, and smooth side wall surfaces can be formed even at room temperature. A semiconductor substrate is placed on a sample stage which is kept at room temperature in a reaction container. A trench is formed in the semiconductor substrate by plasma etching that uses etching gas including oxygen and sulfur hexafluoride, while controlling the gas ratio of oxygen to sulfur hexafluoride so that the gas ratio is from 70% to 100%.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 19, 2020
    Assignee: ABLIC INC.
    Inventors: Akihiro Kikuchi, Takeshi Kuroda, Shintaro Koseki
  • Patent number: 10644370
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 5, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Akihiro Kikuchi, Genro Kato, Kosuke Nishino, Nobuo Ikemoto
  • Publication number: 20200019199
    Abstract: In a power converter including: a first DC-DC converter, an inverter, and a control circuit, a second DC-DC converter that controls an input and an output of a power storage unit is connectable to a DC bus. The control circuit deactivates a reverse power flow suppression function for suppressing a reverse power flow from the inverter to a power system when the second DC-DC converter is not connected to the DC bus and activates the reverse power flow suppression function when the second DC-DC converter is connected to the DC bus.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Kota MAEBA, Akihiro KIKUCHI, Wataru HORIO, Hiroyuki FUJII, Kenji HANAMURA, Tomoki ITO
  • Publication number: 20190341665
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Takahiro BABA, Akihiro KIKUCHI, Genro KATO, Kosuke NISHINO, Nobuo IKEMOTO
  • Publication number: 20190326752
    Abstract: In a power converter, a DC bus is supplied with a DC power from a voltage conversion circuit for regulating a voltage of a power output from a DC power supply, a voltage of the DC power being regulated by the voltage conversion circuit. An inverter converts a DC power on the DC bus into an AC power and supplies the AC power as converted to a power system. A controller controls the inverter. When it is necessary to suppress an output, the controller suppresses the AC power supplied by the inverter to increase a voltage on the DC bus.
    Type: Application
    Filed: January 22, 2018
    Publication date: October 24, 2019
    Inventors: Akihiro KIKUCHI, Kenji HANAMURA, Tomoki ITO
  • Patent number: 10424824
    Abstract: An electronic apparatus includes a substrate and an electrical element mounted on the substrate. The electrical element includes a base material including a first principal surface and a second principal surface that are deformable and flat or substantially flat surfaces and a conductor pattern included on the base material. The electrical element further includes a first connection portion and a second connection portion that connect to a circuit included on the substrate and a transmission line portion located in a position different from positions of the first connection portion and the second connection portion that electrically connects the first connection portion and the second connection portion. The conductor pattern includes a conductor pattern of the first connection portion, a conductor pattern of the second connection portion, a conductor pattern of the transmission line portion, and an electrical-element-side bonding pattern arranged in the transmission line portion.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 24, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Akihiro Kikuchi, Genro Kato, Kosuke Nishino, Nobuo Ikemoto
  • Publication number: 20180166290
    Abstract: Provided is a method of manufacturing a semiconductor device with which a trench shape having vertical, flat, and smooth side wall surfaces can be formed even at room temperature. A semiconductor substrate is placed on a sample stage which is kept at room temperature in a reaction container. A trench is formed in the semiconductor substrate by plasma etching that uses etching gas including oxygen and sulfur hexafluoride, while controlling the gas ratio of oxygen to sulfur hexafluoride so that the gas ratio is from 70% to 100%.
    Type: Application
    Filed: November 16, 2017
    Publication date: June 14, 2018
    Inventors: Akihiro KIKUCHI, Takeshi KURODA, Shintaro KOSEKI
  • Patent number: 9925571
    Abstract: A method of cleaning a substrate processing apparatus including a gas supply part configured to eject a process gas via gas passages formed in the gas supply part, and divided into first and second regions corresponding to first and second in-plane positions of a substrate, respectively, includes cleaning a first one of the gas passages corresponding to the first region with the plasma of the process gas by causing a first flow rate of the process gas supplied to the first region to be lower than a second flow rate of the process gas supplied to the second region and cleaning a second one of the gas passages corresponding to the second region with the plasma by causing a third flow rate of the process gas supplied to the first region to be higher than a fourth flow rate of the process gas supplied to the second region.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Mitsuhiro Tomura
  • Patent number: 9728381
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 8, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai