Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SOURCE-CHANNEL JUNCTION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
    Publication number: 20200006480
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Cheng-Ying HUANG, Tahir GHANI, Jack KAVALIEROS, Anand MURTHY, Harold KENNEL, Gilbert DEWEY, Matthew METZ, Willy RACHMADY, Sean MA, Nicholas MINUTILLO
  • CHANNEL LAYER FORMATION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
    Publication number: 20200006069
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Gilbert DEWEY, Matthew METZ, Willy RACHMADY, Sean MA, Nicholas MINUTILLO, Cheng-Ying HUANG, Tahir GHANI, Jack KAVALIEROS, Anand MURTHY, Harold KENNEL
  • INTEGRATED CIRCUIT STRUCTURES HAVING GERMANIUM-BASED CHANNELS
    Publication number: 20200006492
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Siddharth CHOUKSEY, Glenn GLASS, Anand MURTHY, Harold KENNEL, Jack T. KAVALIEROS, Tahir GHANI, Ashish AGRAWAL, Seung Hoon SUNG
  • CHANNEL LAYER FORMATION FOR III-V METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
    Publication number: 20200006576
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sean MA, Nicholas MINUTILLO, Cheng-Ying HUANG, Tahir GHANI, Jack KAVALIEROS, Anand MURTHY, Harold KENNEL, Gilbert DEWEY, Matthew METZ, Willy RACHMADY
  • METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
    Publication number: 20190334034
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Inventors: Michael JACKSON, Anand MURTHY, Glenn GLASS, Saurabh MORARKA, Chandra MOHAPATRA
  • Methods of forming dislocation enhanced strain in NMOS structures
    Patent number: 10396201
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • SYSTEMS, METHODS AND DEVICES FOR ISOLATION FOR SUBFIN LEAKAGE
    Publication number: 20190189749
    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Benjamin Chu-Kung, Van Le, Seung Hoon Sung, Jack Kavalieros, Ashish Agrawal, Harold Kennel, Siddharth Chouksey, Anand Murthy, Tahir Ghani, Glenn Glass, Cheng-Ying Huang
  • METHODS OF FORMING SELF ALIGNED SPACERS FOR NANOWIRE DEVICE STRUCTURES
    Publication number: 20180358436
    Abstract: Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.
    Type: Application
    Filed: December 24, 2015
    Publication date: December 13, 2018
    Applicant: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn Glass, Anand Murthy, Jun Sung Kang, Seiyon Kim
  • METHODS OF FORMING DOPED SOURCE/DRAIN CONTACTS AND STRUCTURES FORMED THEREBY
    Publication number: 20180261696
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Application
    Filed: December 24, 2015
    Publication date: September 13, 2018
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9876113
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 23, 2018
    Assignee: INTEL CORPORATION
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Semiconductor transistor having a stressed channel
    Patent number: 9735270
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9680016
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 13, 2017
    Assignee: INTEL CORPORATION
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Enhanced dislocation stress transistor
    Patent number: 9660078
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Nanowire transistor with underlayer etch stops
    Patent number: 9614060
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • SURFACE ENCAPSULATION FOR WAFER BONDING
    Publication number: 20170062569
    Abstract: Techniques are disclosed for wafer bonding with an encapsulation layer. A first semiconductor substrate is provided. An encapsulation layer is then formed on top of the first semiconductor substrate. The encapsulation layer is formed of an encapsulation material that creates a stable oxide when exposed to an oxidizing agent. A first bonding layer is formed on top of the encapsulation layer. Next, a second semiconductor substrate is provided. A second bonding layer is formed on top of the second bonding layer. Thereafter, the first semiconductor substrate is bonded to the second semiconductor substrate by attaching the first bonding layer to the second bonding layer.
    Type: Application
    Filed: June 13, 2014
    Publication date: March 2, 2017
    Inventors: Kimin JUN, Willy RACHMADY, Glenn GLASS, Anand MURTHY
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20160336447
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Anand MURTHY, Boyan BOYANOV, Glenn A. GLASS, Thomas HOFFMAN
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20160336446
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffman
  • Semiconductor transistor having a stressed channel
    Patent number: 9490364
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20160284821
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9437710
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffman