Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL
    Publication number: 20220093586
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
  • Transistor structure with indium phosphide channel
    Patent number: 11276694
    Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew Metz, Gilbert Dewey, Nicholas Minutillo, Cheng-Ying Huang, Jack Kavalieros, Anand Murthy, Tahir Ghani
  • Device, method and system for promoting channel stress in a NMOS transistor
    Patent number: 11264501
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS AND PMOS STRUCTURES
    Publication number: 20220059699
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Application
    Filed: October 12, 2021
    Publication date: February 24, 2022
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)
    Patent number: 11257904
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Tahir Ghani, Jack Kavalieros, Anand Murthy, Harold Kennel, Gilbert Dewey, Matthew Metz, Willy Rachmady, Sean Ma, Nicholas Minutillo
  • Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
    Patent number: 11244943
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
  • Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
    Patent number: 11164785
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Ashish Agrawal, Gilbert Dewey, Cheng-Ying Huang, Willy Rachmady, Anand Murthy, Ryan Keech, Cory Bomberger
  • Methods of forming dislocation enhanced strain in NMOS structures
    Patent number: 11107920
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END OF LINE AND METHODS OF FABRICATION
    Publication number: 20210202378
    Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
  • THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING UPPER-LEVEL TRANSISTORS WITH EPITAXIAL SOURCE & DRAIN MATERIAL
    Publication number: 20210202319
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Gilbert Dewey, Cheng-Ying Huang, Willy Rachmady, Anand Murthy, Ryan Keech, Cory Bomberger
  • THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL
    Publication number: 20210202476
    Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Cheng-Ying Huang, Gilbert Dewey, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger, Cory Bomberger, Ryan Keech, Koustav Ganguly, Anand Murthy, Jack Kavalieros
  • Methods of forming doped source/drain contacts and structures formed thereby
    Patent number: 11004978
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • THIN FILM TRANSISTOR STRUCTURES WITH REGROWN SOURCE & DRAIN
    Publication number: 20210036023
    Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
  • GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH TIGHT VERTICAL SPACING
    Publication number: 20200357930
    Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Glenn GLASS, Anand MURTHY, Biswajeet GUHA, Tahir GHANI, Susmita GHOSE, Zachary GEIGER
  • SILICIDE STRUCTURE OF AN INTEGRATED TRANSISTOR DEVICE AND METHOD OF PROVIDING SAME
    Publication number: 20200343343
    Abstract: Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.
    Type: Application
    Filed: February 8, 2018
    Publication date: October 29, 2020
    Applicant: Intel Corporation
    Inventors: Orb Acton, Joseph Steigerwald, Anand Murthy, Scott Maddox, Jenny Hu
  • SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES
    Publication number: 20200313001
    Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ryan KEECH, Benjamin CHU-KUNG, Subrina RAFIQUE, Devin MERRILL, Ashish AGRAWAL, Harold KENNEL, Yang CAO, Dipanjan BASU, Jessica TORRES, Anand MURTHY
  • SOURCE OR DRAIN STRUCTURES WITH VERTICAL TRENCHES
    Publication number: 20200312842
    Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ryan KEECH, Nicholas MINUTILLO, Anand MURTHY, Aaron BUDREVICH, Peter WELLS
  • GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GERMANIUM NANOWIRE CHANNEL STRUCTURES
    Publication number: 20200312981
    Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Cory BOMBERGER, Anand MURTHY, Susmita GHOSE, Zachary GEIGER
  • SOURCE OR DRAIN STRUCTURES WITH LOW RESISTIVITY
    Publication number: 20200312959
    Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Cory BOMBERGER, Anand MURTHY, Suresh VISHWANATH
  • GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING EMBEDDED GESNB SOURCE OR DRAIN STRUCTURES
    Publication number: 20200312960
    Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Cory BOMBERGER, Anand MURTHY, Susmita GHOSE, Siddharth CHOUKSEY