Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9437710
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffman
  • METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
    Publication number: 20160204256
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Application
    Filed: September 26, 2013
    Publication date: July 14, 2016
    Inventors: Michael JACKSON, Anand MURTHY, Glenn GLASS, Saurabh MORARKA, Chandra MOHAPATRA
  • Nanowire transistor with underlayer etch stops
    Patent number: 9385221
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL
    Publication number: 20160133747
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Application
    Filed: December 22, 2015
    Publication date: May 12, 2016
    Inventors: ANAND MURTHY, ROBERT S. CHAU, TAHIR GHANI, KAIZAD R. MISTRY
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20160079423
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Enhanced dislocation stress transistor
    Patent number: 9231076
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9202889
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20150221744
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Enhanced dislocation stress transistor
    Patent number: 9076814
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Nanowire transistor with underlayer etch stops
    Patent number: 9064944
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20150155384
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 4, 2015
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20150108546
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Anand MURTHY, Boyan Boyanov, Glen A. Glass, Thomas Hoffman
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20140284626
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20140264280
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Enhanced dislocation stress transistor
    Patent number: 8779477
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Strained transistor integration for CMOS
    Patent number: 8748869
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Anand Murthy, Brian S. Doyle, Robert Chau
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20130302961
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 14, 2013
    Inventors: Anand Murthy, Boyan Boyanov, Glen A. Glass, Thomas Hoffman
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 8482043
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • STRAINED TRANSISTOR INTEGRATION FOR CMOS
    Publication number: 20130153965
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Application
    Filed: February 11, 2013
    Publication date: June 20, 2013
    Inventors: Boyan Boyanov, Anand Murthy, Brian S. Doyle, Robert Chau
  • Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
    Patent number: 8426858
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer