Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, a pillar comprising a channel material extending vertically through the stack, and a sense device comprising a gate material within the source tier. The gate material of the sense devices is in electrical communication with the channel material of the pillar. Related memory devices, systems, and methods are also described.

Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.

Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o

Abstract: A microelectronic device includes decks comprising alternating levels of a conductive material and an insulative material, the decks comprising pillars including a channel material extending through the alternating levels of the conductive material and the insulative material, a conductive contact between adjacent decks and in electrical communication with the channel material of the adjacent decks, and an oxide material between the adjacent decks, the oxide material extending between an uppermost level of a first deck and a lowermost level of a second deck adjacent to the first deck. Related electronic systems and methods of forming the microelectronic device and electronic systems are also disclosed.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o

Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.