Abstract: Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed.

Abstract: Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed.

Abstract: A method of applying an inhibit bias to an unselected word line when programming a NAND memory device is provided. The method may include ramping the inhibit bias to the unselected word line to a first predetermined voltage and ramping the inhibit bias to the unselected word line to a second predetermined voltage. Ramping of the inhibit bias to the unselected word line to a first predetermined voltage may occur until a boosted channel reaches a leakage limited saturation potential.

Abstract: Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract: Memory arrays and their formation are disclosed. One such memory array has first and second memory cells over a semiconductor, an air gap between the first and second memory cells, and an isolation region within the semiconductor and under the air gap so that the isolation region is aligned with the air gap.

Abstract: Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: A method of applying an inhibit bias to an unselected word line when programming a NAND memory device is provided. The method may include ramping the inhibit bias to the unselected word line to a first predetermined voltage and ramping the inhibit bias to the unselected word line to a second predetermined voltage. Ramping of the inhibit bias to the unselected word line to a first predetermined voltage may occur until a boosted channel reaches a leakage limited saturation potential.

Abstract: Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the control gate. For example, a select gate may be coupled in series with the memory cell and has a first control gate portion formed from the first conductor and a second control gate portion formed from a third conductor. A contact may be formed from the third conductor and coupled in series with the select gate. Other methods and devices are also disclosed.

Abstract: Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.