Patents by Inventor Andrew Bicksler

Andrew Bicksler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of forming field effect transistors including floating gate field effect transistors
    Publication number: 20060258103
    Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.
    Type: Application
    Filed: July 20, 2006
    Publication date: November 16, 2006
    Inventors: Andrew Bicksler, Sukesh Sandhu
  • Minimizing adjacent wordline disturb in a memory device
    Publication number: 20060198222
    Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.
    Type: Application
    Filed: May 4, 2006
    Publication date: September 7, 2006
    Inventors: Paul Rudeck, Andrei Mihnea, Andrew Bicksler
  • Minimizing adjacent wordline disturb in a memory device
    Publication number: 20060198221
    Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.
    Type: Application
    Filed: May 4, 2006
    Publication date: September 7, 2006
    Inventors: Paul Rudeck, Andrei Mihnea, Andrew Bicksler
  • Minimizing adjacent wordline disturb in a memory device
    Publication number: 20060002167
    Abstract: A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Paul Rudeck, Andrei Mihnea, Andrew Bicksler