Patents by Inventor Anthony I. Chou
Anthony I. Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150270284Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Murshed M. Chowdhury, Arvind Kumar, Robert R. Robison
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Patent number: 9064972Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: GrantFiled: March 20, 2014Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Publication number: 20150162438Abstract: A tunneling dielectric layer, a floating gate material layer, and an etch stop layer are formed over a semiconductor fin. After formation of a planarization dielectric layer, a top surface of the floating gate material layer is physically exposed above the semiconductor fin by removing a horizontal portion of the etch stop layer. After removal of the planarization dielectric layer, a semiconductor oxide portion is formed on a horizontal portion of the floating gate material layer. After removal of the etch stop layer, the floating gate material layer is patterned into a floating gate electrode employing the semiconductor oxide portion as a self-aligned etch mask. A control gate dielectric layer and a conductive material layer are deposited and patterned to form a control gate dielectric and a gate electrode.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Applicant: International Business Machines CorporationInventors: Anthony I. Chou, Murshed M. Chowdhury, Arvind Kumar
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Publication number: 20150123190Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.Type: ApplicationFiled: January 7, 2015Publication date: May 7, 2015Inventors: Anthony I. Chou, Arvind Kumar
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Patent number: 8963228Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.Type: GrantFiled: April 18, 2013Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar
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Patent number: 8900961Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: October 19, 2010Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
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Publication number: 20140312404Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.Type: ApplicationFiled: April 18, 2013Publication date: October 23, 2014Applicant: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar
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Publication number: 20140206160Abstract: A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Inventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8779551Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: GrantFiled: June 6, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Publication number: 20140106550Abstract: A method of ion implantation is disclosed. A beam of ions is accelerated to a first energy level. The beam of ions is decelerated from the first energy level to produce a contamination beam of ions via an ion collision process. The ions of the contamination beam are implanted in a substrate to obtain a selected dopant profile in the substrate.Type: ApplicationFiled: October 11, 2012Publication date: April 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Murshed M. Chowdhury, Arvind Kumar, Shreesh Narasimha, Craig M. Sinn
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Publication number: 20140084412Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
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Patent number: 8667448Abstract: Embodiments include a method for providing a local maximum operating voltage on an integrated circuit. The method includes determining a gate-to-contact reliability for each of the plurality of regions and calculating a local maximum voltage for each of the plurality of regions based on the gate-to-contact reliability. Based on a determination that the local maximum voltage in one of the plurality of regions is greater than a maximum voltage, the method includes setting the local maximum operating voltage to the maximum voltage. Based on a determination that the local maximum voltage in one of the plurality of regions is less than the maximum voltage, the method includes setting the local maximum operating voltage to the local maximum voltage.Type: GrantFiled: November 29, 2012Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo
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Publication number: 20130328124Abstract: A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher
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Patent number: 8558313Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: March 21, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Publication number: 20130264679Abstract: A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.Type: ApplicationFiled: April 5, 2012Publication date: October 10, 2013Applicant: International Business Machines CorporationInventors: Arvind Kumar, Anthony I. Chou, Renee T. Mo, Shreesh Narasimha
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Patent number: 8546920Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: October 15, 2012Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 8299519Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.Type: GrantFiled: January 11, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar
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Patent number: 8288826Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: November 7, 2011Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 8232599Abstract: An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.Type: GrantFiled: January 7, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Shreesh Narasimha, Ning Su, Huiling Shang
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Patent number: 8232603Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.Type: GrantFiled: February 9, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha