Abstract: A memory cell is provided for storing a bit. The memory cell includes a capacitor with capacitor electrodes for storing electric charge and a semiconductor switch with a channel region, the electrical conductivity of which is controllable, for connecting the capacitor to a bit line, via which a bit can be written to and read from the memory cell. The channel region and a metallic terminal region connected to one of the capacitor electrodes form a metal-semiconductor junction.

Abstract: A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

Abstract: A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

Abstract: A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.

Abstract: A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.

Abstract: A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.