Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region, a second semiconductor region arranged on the first semiconductor region, a third semiconductor region arranged on the second semiconductor region, a first trench penetrating the second semiconductor region from the third semiconductor region and reaching the first semiconductor region, a first main electrode arranged on the second semiconductor region via a first insulating film, field electrodes arranged via second insulating films in a second trenches that are deeper than the first trench and reach the first semiconductor region. The first main electrode may be arranged between the field electrodes. The field electrodes may be arranged alternately, and the field electrodes that are alternately adjacent to each other may be arranged so that the field electrodes partially overlap with adjacent field electrodes in an alignment direction of the arranging field electrodes in a plan view.

Abstract: An insulating transformer includes an insulation layer, a transformer embedded in the insulation layer, and a capacitor. The transformer includes first and second coils. The first coil includes a first signal terminal and a first ground terminal. The second coil is separated from the first coil in a thickness direction of the insulation layer and includes a second signal terminal and a second ground terminal. The capacitor includes first and second capacitor electrodes. The first capacitor electrode is connected to the first ground terminal of the first coil. The second capacitor electrode is located between the first capacitor electrode and the second coil and connected to the second ground terminal of the second coil. The insulating transformer further includes a first insulation film located between the first coil and the first capacitor electrode, and a second insulation film located between the second coil and the second capacitor electrode.

Abstract: This isolation transformer includes: an isolation layer; a transformer having a first coil and a second coil; and a capacitor having a first capacitor electrode and a second capacitor electrode disposed between the first coil and the second coil. The isolation layer includes a first isolation film in which the first coil is embedded, a second isolation film on the upper surface of the first isolation film, a protective film on the upper surface of the second isolation film, a third isolation film on the upper surface of the protective film, a fourth isolation film on the upper surface of the third isolation film, and a fifth isolation film on the upper surface of the fourth isolation film. The second capacitor electrode is formed between the third isolation film and the fourth isolation film. The second coil is formed between the fourth isolation film and the fifth isolation film.

Abstract: An isolation transformer includes an insulation layer, a transformer, and a capacitor. The transformer includes first and second coils separated from each other in a thickness-wise direction of the insulation layer. The capacitor includes a first capacitor electrode and a second capacitor electrode. The insulation layer includes thin films and interlayer insulation films alternately stacked in the direction. The thin films include first and second thin films separated from each other in the direction. The interlayer insulation films include a first interlayer insulation film located next to the first thin film in the direction and a second interlayer insulation film located next to the second thin film in the direction. The first capacitor electrode is formed between the first thin film and the first interlayer insulation film. The second capacitor electrode is formed between the second thin film and the second interlayer insulation film.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.

Abstract: A semiconductor device includes a semiconductor layer that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor layer, a first insulating portion that is formed on the principal surface of the semiconductor layer so as to cover the first conductive layer and that includes a first insulating layer of at least three or more layers, a second insulating portion that is formed on the first insulating portion, that has a dielectric constant differing from a dielectric constant of the first insulating layer, and that includes a second insulating layer not included in the first insulating portion, and a second conductive layer that is formed on the second insulating portion, that faces the first conductive layer through the first insulating portion and the second insulating portion, and that is connected to a potential differing from a potential of the first conductive layer.

Abstract: This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

Abstract: A semiconductor device includes a semiconductor chip that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor chip and connected to a first potential, a second conductive layer that opposes the first conductive layer of the principal surface in a normal direction and is connected to a second potential higher than the first potential, an insulating layer that is formed between the first conductive layer and the second conductive layer, and a first pad that is formed in a region separated from a region that opposes the second conductive layer in a first direction in a plan view when the semiconductor chip is viewed in the normal direction and that is electrically connected to the first conductive layer.

Abstract: A gate driver includes a low-voltage circuit configured to be actuated by application of a first voltage and a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver also includes a transformer and a capacitor connected in series to the transformer. The low-voltage circuit and the high-voltage circuit are connected by the transformer and the capacitor and configured to transmit a signal through the transformer and the capacitor.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.

Abstract: A semiconductor device includes a chip that has a first main surface on one side and a second main surface on another side, a pn-junction portion that is formed in an interior of the chip such as to extend along the first main surface, a device region that is provided in the first main surface, a first trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in the first main surface, and a second trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in a region further to the device region side than the first trench structure.

Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.

Abstract: An electronic component includes a chip that has a main surface, an insulating layer that is laminated at a thickness exceeding 2200 nm on the main surface and has a first end on the chip side and a second end on an opposite side to the chip, and a resistive film that is arranged inside the insulating layer such as not to be positioned within a thickness range of less than 2200 nm on a basis of the first end and includes an alloy crystal constituted of a metal element and a nonmetal element.

Abstract: A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

Abstract: A semiconductor device includes a semiconductor layer, an element isolation portion that is formed at the semiconductor layer and that defines an element region in the semiconductor layer, and a first contact that is formed in a linear shape along the element isolation portion in a plan view and that is electrically connected to the element isolation portion. The semiconductor device further includes a semiconductor substrate supporting the semiconductor layer and a buried layer formed so as to be contiguous to the semiconductor layer, and the element isolation portion may reach the semiconductor substrate through the buried layer from a front surface of the semiconductor layer.