Patents by Inventor Bungo Tanaka
Bungo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11777027Abstract: A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.Type: GrantFiled: June 29, 2021Date of Patent: October 3, 2023Assignees: SANKEN ELECTRIC CO., LTD., Allegro MicroSystems, LLCInventor: Bungo Tanaka
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Publication number: 20230102799Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: ApplicationFiled: December 1, 2022Publication date: March 30, 2023Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
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Publication number: 20230088792Abstract: A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Applicant: SANKEN ELECTRIC CO., LTD.Inventors: Taro KONDO, Shunsuke FUKUNAGA, Bungo TANAKA, Jun YASUHARA
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Publication number: 20230083880Abstract: A semiconductor device includes a semiconductor layer, an element isolation portion that is formed at the semiconductor layer and that defines an element region in the semiconductor layer, and a first contact that is formed in a linear shape along the element isolation portion in a plan view and that is electrically connected to the element isolation portion. The semiconductor device further includes a semiconductor substrate supporting the semiconductor layer and a buried layer formed so as to be contiguous to the semiconductor layer, and the element isolation portion may reach the semiconductor substrate through the buried layer from a front surface of the semiconductor layer.Type: ApplicationFiled: March 3, 2021Publication date: March 16, 2023Applicant: ROHM CO., LTD.Inventor: Bungo TANAKA
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Publication number: 20230058805Abstract: An electronic component of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities. The first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, and the barrier layer may include a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.Type: ApplicationFiled: February 22, 2021Publication date: February 23, 2023Applicant: ROHM CO., LTD.Inventor: Bungo TANAKA
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Patent number: 11545454Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: GrantFiled: April 14, 2021Date of Patent: January 3, 2023Assignee: ROHM CO., LTD.Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
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Publication number: 20220416078Abstract: A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Applicants: SANKEN ELECTRIC CO., LTD., Allegro MicroSystems, LLCInventor: Bungo TANAKA
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Publication number: 20220367603Abstract: A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.Type: ApplicationFiled: September 30, 2020Publication date: November 17, 2022Inventor: Bungo TANAKA
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Publication number: 20220302028Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.Type: ApplicationFiled: June 7, 2022Publication date: September 22, 2022Applicant: ROHM CO., LTD.Inventor: Bungo TANAKA
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Patent number: 11393752Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.Type: GrantFiled: March 17, 2020Date of Patent: July 19, 2022Assignee: ROHM CO., LTD.Inventor: Bungo Tanaka
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Publication number: 20210305157Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Inventor: Bungo TANAKA
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Patent number: 11094443Abstract: An electronic component includes a first insulating layer, a high-voltage electrode formed on the first insulating layer, a low-voltage electrode formed on the first insulating layer so as to be spaced from the high-voltage electrode, and an uneven structure formed in a region between the high-voltage electrode and the low-voltage electrode along a surface of the first insulating layer.Type: GrantFiled: November 7, 2017Date of Patent: August 17, 2021Assignee: ROHM CO., LTD.Inventors: Bungo Tanaka, Yasushi Hamazawa
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Publication number: 20210233882Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
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Patent number: 11062992Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.Type: GrantFiled: August 30, 2019Date of Patent: July 13, 2021Assignee: ROHM CO., LTD.Inventor: Bungo Tanaka
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Patent number: 11011489Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: GrantFiled: April 7, 2020Date of Patent: May 18, 2021Assignee: ROHM CO., LTD.Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
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Patent number: 11004931Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first electrode, and a first insulating film. The first electrode extends in a first direction and is provided inside the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode, a thickness of the first insulating film in a direction from the first electrode toward the semiconductor layer increasing in stages along the first direction. The first insulating film has three or more mutually-different thicknesses.Type: GrantFiled: August 30, 2017Date of Patent: May 11, 2021Assignee: Kabushiki Kaisha ToshibaInventors: Shunsuke Nitta, Takeru Matsuoka, Shunsuke Katoh, Masatoshi Arai, Shinya Ozawa, Bungo Tanaka
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Publication number: 20200303304Abstract: An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Applicant: ROHM CO., LTD.Inventor: Bungo TANAKA
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Publication number: 20200235064Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: ApplicationFiled: April 7, 2020Publication date: July 23, 2020Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
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Patent number: 10651144Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.Type: GrantFiled: September 5, 2019Date of Patent: May 12, 2020Assignee: ROHM CO., LTD.Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
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Patent number: 10622443Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.Type: GrantFiled: July 20, 2016Date of Patent: April 14, 2020Assignee: ROHM CO., LTD.Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji