Patents by Inventor Bungo Tanaka

Bungo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075486
    Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 5, 2020
    Inventor: Bungo TANAKA
  • Publication number: 20190393177
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
  • Patent number: 10453816
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 22, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Publication number: 20180240867
    Abstract: According to an embodiment, a semiconductor device includes a semiconductor layer, a first electrode, and a first insulating film. The first electrode extends in a first direction and is provided inside the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode, a thickness of the first insulating film in a direction from the first electrode toward the semiconductor layer increasing in stages along the first direction. The first insulating film has three or more mutually-different thicknesses.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 23, 2018
    Inventors: Shunsuke Nitta, Takeru Matsuoka, Shunsuke Katoh, Masatoshi Arai, Shinya Ozawa, Bungo Tanaka
  • Patent number: 10026695
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: July 17, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Bungo Tanaka
  • Publication number: 20180130587
    Abstract: An electronic component includes a first insulating layer, a high-voltage electrode formed on the first insulating layer, a low-voltage electrode formed on the first insulating layer so as to be spaced from the high-voltage electrode, and an uneven structure formed in a region between the high-voltage electrode and the low-voltage electrode along a surface of the first insulating layer.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 10, 2018
    Applicant: ROHM CO., LTD.
    Inventors: Bungo TANAKA, Yasushi HAMAZAWA
  • Publication number: 20180102308
    Abstract: In some embodiments, a semiconductor device includes a semiconductor chip including a first terminal, a second terminal and a third terminal, a frame electrically coupled to the second terminal, the frame mounting the semiconductor chip, a first conductor including a chip connection electrically coupled to the first terminal, a first connection connecting to the chip connection and protruding from the chip connection, and a second connection connecting to the chip connection, protruding from the chip connection, and being provided physically spaced from the first connection. The semiconductor device further includes a second conductor electrically coupled to the third terminal.
    Type: Application
    Filed: March 1, 2017
    Publication date: April 12, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya NISHIWAKI, Shunsuke KATOH, Masatoshi ARAI, Chikako YOSHIOKA, Bungo TANAKA, Shinya OZAWA, Takahiro KAWANO
  • Patent number: 9941127
    Abstract: A semiconductor includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a gate electrode. The gate electrode has a first portion arranged with the second semiconductor region in a direction perpendicular to a first direction extending from the first electrode to the first semiconductor region, and has a second portion on the first portion. The semiconductor also includes a gate insulating layer between the gate electrode and each of the three semiconductor regions. The gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion. The second portion of the gate electrode protrudes in an upward direction from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the first portion of the gate electrode.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Bungo Tanaka, Norio Yasuhara
  • Publication number: 20180090461
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 29, 2018
    Applicant: ROHM CO., LTD.
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
  • Publication number: 20170271451
    Abstract: A semiconductor device includes a first-conductivity type first semiconductor region, a gate electrode extending inwardly of the first semiconductor region, a gate insulation layer interposed between the gate electrode and the first semiconductor region, a second-conductivity type second semiconductor region on the first semiconductor region, a first-conductivity type third semiconductor region on selected portions of second semiconductor region, a second-conductivity type fourth semiconductor region on the first semiconductor region and spaced from the second semiconductor region, a first-conductivity type fifth semiconductor region on the fourth semiconductor region, a first insulation layer on the third and fifth semiconductor regions and extending over the gate electrode, a first electrode on the first insulation layer, and a first insulation portion extending between the second and fourth semiconductor regions.
    Type: Application
    Filed: August 30, 2016
    Publication date: September 21, 2017
    Inventors: Kenichi MATSUSHITA, Norio YASUHARA, Bungo TANAKA
  • Patent number: 9653557
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Yuichi Oshino, Keiko Kawamura, Bungo Tanaka
  • Publication number: 20170047444
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided on the second semiconductor region; a gate electrode including: a first portion including polycrystalline silicon and arranged. with the second semiconductor region in a second.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 16, 2017
    Inventors: Bungo Tanaka, Norio Yasuhara
  • Publication number: 20160336277
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, a wiring having copper as a main component and formed above the insulating film, and a barrier metal film having a higher modulus of rigidity than copper and interposed between the insulating film and the wiring. The barrier metal film may have a lower thermal expansion coefficient than copper.
    Type: Application
    Filed: May 12, 2016
    Publication date: November 17, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Bungo TANAKA
  • Publication number: 20160329399
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
  • Patent number: 9425203
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: August 23, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
  • Patent number: 9391070
    Abstract: A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than the
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: July 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Bungo Tanaka
  • Patent number: 9324816
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Yuuichi Oshino, Bungo Tanaka
  • Publication number: 20160079235
    Abstract: A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than the
    Type: Application
    Filed: February 26, 2015
    Publication date: March 17, 2016
    Inventors: Tomoko MATSUDAI, Tsuneo Ogura, Bungo Tanaka
  • Publication number: 20160064536
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a first gate electrode, a first region, and a second region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region. The first region is provided in the second semiconductor region. The first region is positioned between the first semiconductor region and the third semiconductor region. The second region is provided in the second semiconductor region. The second region is positioned between the first region and the gate electrode. A carrier density of the first conductivity type in the second region is higher than a carrier density of the first conductivity type in the first region.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 3, 2016
    Inventors: Bungo Tanaka, Tomoko Matsudai, Yuuichi Oshino
  • Patent number: RE47292
    Abstract: The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Yoneda, Bungo Tanaka