Patents by Inventor Bungo Tanaka

Bungo Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160035840
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 4, 2016
    Inventors: Tomoko Matsudai, Yuuichi Oshino, Bungo Tanaka
  • Publication number: 20150279848
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 1, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
  • Publication number: 20150255629
    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductive type having a first side and an opposed second side; a second semiconductor layer of a second conductive type formed on the first side; a third semiconductor layer of a second conductive type partially formed in the second semiconductor layer; a fourth semiconductor layer of a first conductive type formed between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer facing the third semiconductor layer, the fourth semiconductor layer including a first region which has a first dopant concentration and a second region which has a second dopant concentration higher than the first dopant concentration; a fifth semiconductor layer of a first conductive type formed on the second side; and a conductor contacting the first semiconductor layer, the second semiconductor layer and the third semiconductor layer via an insulation film.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 10, 2015
    Inventors: Ryohei GEJO, Bungo TANAKA
  • Patent number: 9082654
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 14, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
  • Publication number: 20140374791
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.
    Type: Application
    Filed: March 3, 2014
    Publication date: December 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko MATSUDAI, Yuichi OSHINO, Keiko KAWAMURA, Bungo TANAKA
  • Publication number: 20140353737
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 4, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Kunihiko IWAMOTO, Bungo TANAKA, Michihiko MIFUJI
  • Patent number: 8698203
    Abstract: A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Bungo Tanaka
  • Patent number: 8404559
    Abstract: A semiconductor device production method according to the present invention includes the steps of: forming a LOCOS oxide film in a surface of a silicon layer by a LOCOS method; forming an impurity region in the silicon layer by introducing an impurity into the silicon layer; and sequentially removing parts of the LOCOS oxide film and the silicon layer to form a trench for isolation of the impurity region after the formation of the LOCOS oxide film and the impurity region.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: March 26, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Bungo Tanaka
  • Publication number: 20130026542
    Abstract: A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: ROHM CO., LTD.
    Inventor: Bungo TANAKA
  • Publication number: 20120132984
    Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Michihiko Mifuji, Yuichi Nakao, Toshikazu Mizukoshi, Bungo Tanaka, Taku Shibaguchi, Gentaro Morikawa
  • Publication number: 20100096721
    Abstract: A semiconductor device production method according to the present invention includes the steps of: forming a LOCOS oxide film in a surface of a silicon layer by a LOCOS method; forming an impurity region in the silicon layer by introducing an impurity into the silicon layer; and sequentially removing parts of the LOCOS oxide film and the silicon layer to form a trench for isolation of the impurity region after the formation of the LOCOS oxide film and the impurity region.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 22, 2010
    Applicant: ROHM CO., LTD
    Inventor: Bungo Tanaka
  • Patent number: 7525133
    Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: April 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Ohta, Bungo Tanaka
  • Publication number: 20090079006
    Abstract: A semiconductor apparatus includes: a semiconductor device including a semiconductor layer, a first metal main electrode provided on the semiconductor layer and having a first region and a second region, and a metal gate interconnect provided on the semiconductor layer and insulated from and interposed between the first region and the second region; a lead; and a conductive member made of a metal and connecting the first metal main electrode to the lead. The conductive member is bonded to the first region and the second region so as to cover the metal gate interconnect, and the conductive member has a recess on its lower surface above the metal gate interconnect to be spaced from the metal gate interconnect.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 26, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Bungo TANAKA, Akio TAKANO
  • Patent number: 7358564
    Abstract: A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type is formed in the base region. A drain region of the second conduction type is formed apart from the source region in the semiconductor layer. A gate electrode is formed on a gate insulator above the semiconductor layer between the source region and the drain region. A first interlayer insulator is formed on the semiconductor layer to cover the gate electrode. A short electrode is formed to short the base region and the source region. A second interlayer insulator is formed to cover the first interlayer insulator and the short electrode.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: April 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Publication number: 20070145416
    Abstract: A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Ohta, Bungo Tanaka
  • Publication number: 20060197146
    Abstract: A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type is formed in the base region. A drain region of the second conduction type is formed apart from the source region in the semiconductor layer. A gate electrode is formed on a gate insulator above the semiconductor layer between the source region and the drain region. A first interlayer insulator is formed on the semiconductor layer to cover the gate electrode. A short electrode is formed to short the base region and the source region. A second interlayer insulator is formed to cover the first interlayer insulator and the short electrode.
    Type: Application
    Filed: April 27, 2005
    Publication date: September 7, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 7045856
    Abstract: In a semiconductor layer of the first conductivity type, a first diffusion region of the second conductivity type is formed which includes a low resistance layer and a high resistance layer. This semiconductor layer of the first conductivity type has its thickness that is less than or equal to the lateral width of the high resistance layer.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 7019361
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20050258478
    Abstract: In a semiconductor layer of the first conductivity type, a first diffusion region of the second conductivity type is formed which includes a low resistance layer and a high resistance layer. This semiconductor layer of the first conductivity type has its thickness that is less than or equal to the lateral width of the high resistance layer.
    Type: Application
    Filed: July 19, 2004
    Publication date: November 24, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshitaka Hokomoto, Akio Takano, Bungo Tanaka
  • Patent number: 6958514
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato