Abstract: There are provided a ferroelectric RAM (Random Access Memory) device and a control method thereof. In the device, a data input buffer circuit senses a transition of input data and generates a data transition detection signal. Further, a plate pulse generator generates a single pulse to store first logic data among applied data at an enable section of a plate line, and to store second logic data opposite to the first logic data at a disable section of the plate line, where the single pulse enables the plate line connected to a memory cell in response to the data transition detection signal and then disables it after lapse of a given time. Thus, a stabilized write operation can be provided and a control of the ferroelectric RAM device can be simplified.

Abstract: A ferroelectric random access memory (FRAM) device and a driving method thereof are provided that reduce data loss in an operation of the FRAM device. A power supply supplies a power source to the memory device. A power detection circuit detects a voltage level of the power supply and generates a detection signal when the power source has an off state. In an internal chip enable (ICE) signal generation circuit, an ICE signal is disabled to stop operation of the memory device when the ICE signal is enabled and the detection signal is applied at a first time point, and an enabled state of the ICE signal is maintained when the detection signal is applied at a second time point, wherein the operation of the FRAM device continues by control signals generated from the ICE signal.

Abstract: A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

Abstract: A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

Abstract: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

Abstract: A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

Abstract: Disclosed is a word line driver circuit and a driving method thereof. An input to the circuit has a ground voltage level during a non-selected operating mode and, as the output signal of a word line decoding circuit, is applied at a power source voltage level during a selected operating mode. The output of the circuit has a ground voltage level during the non-selected operating mode and applies a higher voltage than the power source voltage to a word line connected to a memory cell during the selected operating mode. Optionally, a capacitor boosts the output voltage during the selected operating mode.

Abstract: A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

Abstract: A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

Abstract: A reference voltage generating apparatus and a driving method therefor are provided. The method of driving the reference voltage generating apparatus for supplying a reference voltage to read data from a ferroelectric memory cell including a ferroelectric capacitor and an access transistor comprises: re-storing, in a reference cell, data equal to data stored in the reference cell, in response to a first control signal, and generating a reference voltage, in the re-stored reference cell, in response to a second control signal, to compare the reference voltage with a voltage corresponding to data stored in the ferroelectric memory cell and to read the data stored in the ferroelectric memory cell. The reference cell includes a ferroelectric capacitor and an access transistor.

Abstract: There are provided a ferroelectric RAM (Random Access Memory) device and a control method thereof. In the device, a data input buffer circuit senses a transition of input data and generates a data transition detection signal. Further, a plate pulse generator generates a single pulse to store first logic data among applied data at an enable section of a plate line, and to store second logic data opposite to the first logic data at a disable section of the plate line, where the single pulse enables the plate line connected to a memory cell in response to the data transition detection signal and then disables it after lapse of a given time. Thus, a stabilized write operation can be provided and a control of the ferroelectric RAM device can be simplified.

Abstract: An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first input to the sense amplifier circuit in comparison to a reference voltage provided as a second input to the sense amplifier circuit. A bit line electrically can be coupled to the memory cell circuit and indirectly electrically coupled to the first input of the sense amplifier circuit and configured to provide the stored data to the sense amplifier circuit. A reference voltage line can also be indirectly electrically coupled to the second input of the sense amplifier circuit and configured to provide the reference voltage to the sense amplifier circuit.

Abstract: A ferroelectric RAM (Random Access Memory) device includes at least one memory cell constructed of one access transistor operating by a word line enable signal, and one ferroelectric capacitor connected between a bit line and the access transistor. The device has a cell array structure based on a repeated array of the memory cells. The device also includes a word line driver suitable for a high integration and reducing power consumption. The driving method in the ferroelectric RAM device generates a word line enable signal having a level of power source voltage, to read and write data. The method has advantages of being suitable for a high integration, enhancing an operating speed and reducing power consumption and providing stabilized read and write operations.

Abstract: We describe and claim a ferroelectric memory device includes a plurality of memory cells, each memory cell comprising a ferroelectric capacitor and a transistor, a plate line drive unit capable of providing a first voltage to the memory cell array in response to a plate line drive signal, and a reference voltage generating device. The reference voltage generating includes a reference cell block having a plurality of reference cells, each reference cell including a ferroelectric capacitor and a transistor, and a reference plate line drive to provide a reference plate line voltage to at least one reference cell in response to a plate line drive signal and a reference voltage generation signal, where each reference cell generates a reference voltage in response to the reference plate line voltage.

Abstract: Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

Abstract: Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

Abstract: A nonvolatile semiconductor memory device is provided, comprising a nonvolatile memory cell array which has a one-time programming region accessed in response to a first decoding signal and a normal region accessed in response to a second decoding signal. The device performs a read operation and a write operation. The device further comprises (a) a data write circuit writing data in the nonvolatile memory cell array in response to a write enable signal during the write operation; (b) a data read circuit reading data output from the nonvolatile memory cell array in response to a sense amplifier enable signal during the read operation; and (c) a control means activating the sense amplifier enable signal when the first decoding signal is generated and comparing data output from the data read circuit to generate the write enable signal during the write operation.

Abstract: A ferroelectric random access memory device according to the present invention includes a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

Abstract: A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.