Abstract: Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.

Abstract: A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

Abstract: An integrated circuit memory device can include a memory cell circuit configured to store data and a sense amplifier circuit configured to sense and amplify the stored data provided as a first input to the sense amplifier circuit in comparison to a reference voltage provided as a second input to the sense amplifier circuit. A bit line electrically can be coupled to the memory cell circuit and indirectly electrically coupled to the first input of the sense amplifier circuit and configured to provide the stored data to the sense amplifier circuit. A reference voltage line can also be indirectly electrically coupled to the second input of the sense amplifier circuit and configured to provide the reference voltage to the sense amplifier circuit.

Abstract: A ferroelectric memory device comprises a plurality of parallel word lines extending along a first direction, a plurality of parallel bit lines extending along a second direction transverse to the first direction, and a plurality of parallel plate lines extending along the first direction. A plurality of memory cells is arranged in rows and columns along the respective first and second directions, each of the memory cells including a transistor coupled to one of the word lines and to one of the bit lines and a ferroelectric capacitor connected to the transistor and to one of the plate lines such cells in respective rows are connected to respective word lines and that the ferroelectric capacitors of first and second subsets of a row of memory cells are connected to respective first and second plate lines.

Abstract: A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, a floating condition in the plate lines when the main word line is unselected can be prevented.

Abstract: A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

Abstract: A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

Abstract: A ferroelectric memory device comprises a plurality of parallel word lines extending along a first direction, a plurality of parallel bit lines extending along a second direction transverse to the first direction, and a plurality of parallel plate lines extending along the first direction. A plurality of memory cells is arranged in rows and columns along the respective first and second directions, each of the memory cells including a transistor coupled to one of the word lines and to one of the bit lines and a ferroelectric capacitor connected to the transistor and to one of the plate lines such cells in respective rows are connected to respective word lines and that the ferroelectric capacitors of first and second subsets of a row of memory cells are connected to respective first and second plate lines.

Abstract: A redundancy circuit for a semiconductor memory device. The redundancy circuit includes redundancy memory cells and a redundancy word line decoder. The redundancy word line decoder has a fuse circuit that includes fuses and an output signal. The output signal is in one of three states depending on input signals. The fuse circuit controls a cutting of the fuses in accordance with the input signals so as to replace defective normal memory cells with the redundancy memory cells depending on a type of defect experienced by the defective normal memory cells.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: In a ferroelectric random access memory (FRAM) device of the present invention, an address transition detection circuit generates a pulse signal in response to a transition of a row address latched in an address latch circuit, and a flag signal generating circuit generates a chip enable flag signal in response to an external chip enable signal. A delay circuit delays the pulse signal for a predetermined time. After the external chip enable signal is enabled, a controller controls a row decoder circuit in a disabled state when the external chip enable signal is disabled during a delay time of the delay circuit, and controls the flag signal generating circuit to disable the chip enable flag signal. The reliability of the FRAM device is therefore improved by providing it with noise immunity, as when the external chip enable signal is improperly enabled.

Abstract: A nonvolatile memory device comprises a plate line driving circuit having a hierarchical word line structure. The plate line driving circuit is coupled to plate lines corresponding to a main word line. The plate line driving circuit transmits a plate line drive signal to the plate lines when the main word line is selected, and connects the plate lines to the main word line when the main word line is unselected. Therefore, a floating condition in the plate lines when the main word line is unselected can be prevented.

Abstract: A reference circuit, which is applied to a ferroelectric random access memory device, includes a polarization state detection circuit having dummy cells with ferroelectric capacitors. The detection circuit checks polarization states of the ferroelectric capacitor in the dummy cells using dumping voltages of different levels, and generates pass/fail signals as a check result. The generated pass/fail signals are decoded, using themselves as selection information for selecting one of reference voltages, of different levels, which are generated from a reference voltage generation circuit. Thus, it is possible to generate an optimal reference voltage, which senses a ferroelectric capacitor polarization state that is changed with time.

Abstract: In a ferroelectric random access memory (FRAM) device of the present invention, an address transition detection circuit generates a pulse signal in response to a transition of a row address latched in an address latch circuit, and a flag signal generating circuit generates a chip enable flag signal in response to an external chip enable signal. A delay circuit delays the pulse signal for a predetermined time. After the external chip enable signal is enabled, a controller controls a row decoder circuit in a disabled state when the external chip enable signal is disabled during a delay time of the delay circuit, and controls the flag signal generating circuit to disable the chip enable flag signal. The reliability of the FRAM device is therefore improved by providing it with noise immunity, as when the external chip enable signal is improperly enabled.

Abstract: Disclosed is a ferroelectric random access memory having a reference voltage supplying circuit with a capacitor coupling structure. The reference voltage supplying circuit including a coupling capacitor and switching transistors configured on the basis of the capacitor coupling structure. According to the reference voltage supplying circuit of the present invention, voltages on bit lines coupled to a ferroelectric memory cell and to the reference voltage supplying circuit, respectively, are simultaneously activated. Therefore, a stable sensing margin can be secured even though power noise arises during the read operation.

Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.

Abstract: Disclosed herein is a ferroelectric random access memory device that includes a word line, a plate line corresponding to the word line, a plurality of bit lines, and a plurality of memory cells arranged at intersections of the word line and the bit lines. A first NMOS transistor couples and decouples one end of the plate line to the word line responsive to a first switch control signal. A second NMOS transistor couples or decouples the other end of the plate line to a reference voltage responsive to a second switch control signal.

Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.

Abstract: Disclosed is a ferroelectric random access memory having increased endurance and educed power consumption. The ferroelectric random access memory device comprises a bit line precharge circuit for precharging each of the bit lines to a first voltage level, a pulse supply circuit for supplying a first voltage pulse signal to a first electrode of the ferroelectric capacitor corresponding to a selected one of the memory cells for allowing the ferroelectric capacitor to polarize in a predetermined direction, and a drive signal generation circuit for generating two complementary drive signals which vary from a first voltage level to a second voltage level.