Patents by Inventor Chan Lim

Chan Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004814
    Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-il Choi, Kwangjin Moon, Sujeong Park, JuBin Seo, Jin Ho An, Dong-chan Lim, Atsushi Fujisaki
  • Publication number: 20210132480
    Abstract: An image projection device includes: a panel unit configured to emit light rays; a projection optical system configured to receive the light rays emitted from the panel unit and to refract the light rays; a reflection unit having a reflection surface for receiving the light rays refracted by the projection optical system and reflecting the light rays; and a screen unit configured to display an image upon receiving the light rays reflected from the reflection surface. The panel unit, the projection optical system, the reflection unit, and the screen unit are arranged such that a distance of a shortest path among paths extending from the panel unit to the reflection unit through the projection optical system along a predetermined linear axis is longer than a distance of a longest path among paths extending from the reflection unit to the screen unit along the predetermined linear axis.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Inventors: Dong Youb SINN, Yong Woo BAE, Seung Ho SHIN, Jae Hwang YU, Hak Soon LEE, Guk Chan LIM, Ku Ik CHUNG, Jin Yong HAN
  • Patent number: 10950578
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Seung Lee, Kwang-Jin Moon, Tae-Seong Kim, Dae-Suk Lee, Dong-Chan Lim
  • Publication number: 20210061991
    Abstract: Disclosed are: a thermoplastic elastomer resin composition comprising a thermoplastic elastomer resin and, as a reactive additive, a compound containing one or more isocyanurate functional groups; a molded product comprising the same.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 4, 2021
    Applicant: SAMYANG CORPORATION
    Inventors: Jae-Kwan KWON, Jin YOO, Cheol-Han LEE, Yong-Chan LIM, Sang-Hyun PARK
  • Publication number: 20210066289
    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.
    Type: Application
    Filed: April 17, 2020
    Publication date: March 4, 2021
    Inventors: Sunyoung NOH, Wandon KIM, Hyunbae LEE, Donggon YOO, Dong-Chan LIM
  • Publication number: 20210062377
    Abstract: Disclosed is a melt-blown fiber web with improved concentration force and elasticity, whereby a melt-blown fabric is cut and sealed at predetermined intervals using knives having arbitrary patterns so that concentration force and elasticity of the melt-blown fiber web can be improved without degrading the inherent function of the fiber web. Further disclosed are a method and apparatus for manufacturing the melt-blown fiber web. The melt-blown fiber web includes thermoplastic filaments, wherein cutting portions and sealing portions are arranged on top and bottom surfaces of the fiber web at predetermined intervals along a thickness of the fiber web so that a concentration force and elasticity of the fiber web are improved.
    Type: Application
    Filed: October 13, 2020
    Publication date: March 4, 2021
    Inventors: Min Su Kim, Jung Wook Lee, Jae Chan Lim, Won Jin Seo, Hyeon Ho Kim, Jong Hyuk Cha, Ki Wook Yang, Bong Jik Lee
  • Publication number: 20210066386
    Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.
    Type: Application
    Filed: April 22, 2020
    Publication date: March 4, 2021
    Inventors: Hakseung Lee, Ho-Jin Lee, Dong-Chan Lim, Jinnam Kim, Kwangjin Moon
  • Patent number: 10898977
    Abstract: A system for generating rules inserted into at least one pattern board including: a controller configured to generate at least one shape diagram, the controller also configured to determine number and measurement of crease rules to be generated based on the at least one shape diagram; a cutting station configured to receive and cut a first crease rule into the number and measurement of the crease rules; and a sorter configured to receive the crease rules from the cutting station and sort the crease rules according to the measurement of the crease rules, wherein the sorted crease rules are inserted into each of the at least one pattern board along with a cutting rule shaped by each of at least one bender.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 26, 2021
    Assignee: SEOUL LASER DIEBOARD SYSTEM CO., LTD.
    Inventor: Kyong Chan Lim
  • Patent number: 10847226
    Abstract: A semiconductor device includes a memory string coupled between a common source line and a bit line, the memory string including at least one first selection transistor, a plurality of memory cells, and a plurality of second selection transistors. The semiconductor device also includes selection lines respectively coupled to the second selection transistors. The semiconductor device further includes a control logic circuit configured to float a first group of selection lines from among the selection lines at a first time and configured to float a second group of selection lines from among the selection lines at a second time different from the first time.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Jun Kim, Gae Hun Lee, Hea Jong Yang, Chan Lim, Min Kyu Jeong
  • Patent number: 10837133
    Abstract: Disclosed is a melt-blown fiber web with improved concentration force and elasticity, whereby a melt-blown fabric is cut and sealed at predetermined intervals using knives having arbitrary patterns so that concentration force and elasticity of the melt-blown fiber web can be improved without degrading the inherent function of the fiber web. Further disclosed are a method and apparatus for manufacturing the melt-blown fiber web. The melt-blown fiber web includes thermoplastic filaments, wherein cutting portions and sealing portions are arranged on top and bottom surfaces of the fiber web at predetermined intervals along a thickness of the fiber web so that a concentration force and elasticity of the fiber web are improved.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 17, 2020
    Assignees: Hyundai Motor Company, Kia Motor Company, Iksung Co., Ltd.
    Inventors: Min Su Kim, Jung Wook Lee, Jae CHan Lim, Won Jin Seo, Hyeon Ho Kim, Jong Hyuk Cha, Ki Wook Yang, Bong Jik Lee
  • Publication number: 20200357690
    Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju Bin SEO, Ju-Il CHOI, Atsushi FUJISAKI
  • Patent number: 10763163
    Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-jeong Park, Dong-chan Lim, Kwang-jin Moon, Ju-bin Seo, Ju-il Choi, Atsushi Fujisaki
  • Publication number: 20200273780
    Abstract: A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.
    Type: Application
    Filed: November 8, 2019
    Publication date: August 27, 2020
    Inventors: Kwang Wuk Park, Sung Dong Cho, Eun Ji Kim, Hak Seung Lee, Dae Suk Lee, Dong Chan Lim, Sang Jun Park
  • Publication number: 20200262992
    Abstract: Provided are a method for preparing a unidirectionally aligned discontinuous fiber reinforcement composite material, a unidirectionally aligned discontinuous fiber reinforcement composite material, and a sandwich structure. The method for preparing a unidirectionally aligned discontinuous fiber reinforcement composite material comprises discontinuously aligning short fibers on a polymer substrate in one direction by using an air-laid method.
    Type: Application
    Filed: August 17, 2018
    Publication date: August 20, 2020
    Inventors: Seung-Hyun AHN, Kyung-Seok HAN, Sung-Chan LIM, Hee-June KIM
  • Publication number: 20200198082
    Abstract: Method and system, including: a strip of metallic material used by a bender to produce the 3-D signage; a sanding unit coupled to the bender and configured to sand away any dirt, oil, or other undesirable material attaching to the strip of metallic material; and a controller configured to make a measurement of how fast the strip of metallic material is feeding into the bender, and to control an operating speed of the sanding unit based on the measurement.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventor: Kyong Chan LIM
  • Publication number: 20200189027
    Abstract: Laser cutting a dieboard using a laser cutting system, including: setting a width of material to be removed from the dieboard using the laser cutting system; capturing an image of the width of the material removed by the laser cutting system using at least one image capture unit; measuring the captured width of the material captured on the image using the at least one image capture unit; and comparing the measured width of the material to the set width of the material, and moving a laser head of the laser cutting system up and down to adjust a focal length of the laser cutting system and moving the laser head of the laser cutting system sideways to adjust a speed of the laser head, until the measured width and the set width are substantially similar.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Inventor: Kyong Chan LIM
  • Publication number: 20200161277
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.
    Type: Application
    Filed: June 4, 2019
    Publication date: May 21, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hak-Seung LEE, Kwang-Jin Moon, Tae-Seong Kim, Dae-Suk Lee, Dong-Chan Lim
  • Publication number: 20200156158
    Abstract: The present invention relates to silver particles capable of having a uniform particle distribution, preventing agglomeration of a powder, and significantly improving dispersibility, the silver particles each having pores therein, and to a manufacturing method therefor and, more specifically, to a manufacturing method for silver particles, the method comprising a silver-complex forming step, a silver slurry preparing step, and a silver particle obtaining step, and to silver particles manufactured therefrom.
    Type: Application
    Filed: June 4, 2018
    Publication date: May 21, 2020
    Inventors: Sangwoo KIM, Chiho YOON, Youngho LEE, Jong Chan LIM, Moohyun LIM, Wonjun JO
  • Publication number: 20200144158
    Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.
    Type: Application
    Filed: April 17, 2019
    Publication date: May 7, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Bin SEO, Su-Jeong PARK, Tae-Seong KIM, Kwang-Jin MOON, Dong-Chan LIM, Ju-Il CHOI
  • Publication number: 20200075524
    Abstract: A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 5, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ju Bin SEO, Dong Hoon LEE, Ju Il CHOI, Su Jeong PARK, Dong Chan LIM