Abstract: A semiconductor structure includes a skip via disposed on a metal line of a first metallization layer, and a dielectric layer disposed on sidewalls of the skip via to define an opening. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.

Abstract: A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.

Abstract: A semiconductor device includes a nanostructure field effect transistor (FET). The FET includes a gate and a source or drain (S/D) region. The FET also includes a backside S/D contact connected to a top surface of the S/D region. The backside S/D contact includes a lateral portion upon the top surface of the S/D region. The lateral portion further laterally extends adjacent to or past the first S/D region. The backside S/D contact includes a vertical portion that extends vertically downward from the lateral portion below the bottom surface of the substrate layer. The FET also includes a backside S/D mushroom that extends vertically downward from the vertical portion.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring and a second level of interconnect wiring having a bilayer metal arrangement incorporating via elements, the second level of interconnect wiring electrically connected to the first level of interconnect wiring. In one example, the bilayer metal arrangement of the second level of interconnect wiring includes a first row of bilayer metals and a second row of bilayer metals disposed over the first row of bilayer metals. In another example, the bilayer metal arrangement of the second level of interconnect wiring includes a cap dielectric material for isolation from the first row of the bilayer metal. In yet another embodiment, the bilayer metal arrangement of the second level of interconnect wiring includes a metal bridge.

Abstract: A semiconductor structure comprises a source/drain region, a spacer layer on a first side of the source/drain region, a contact on a top surface of the source/drain region, and a via connected to a portion of the contact at a second side of the source/drain region, the second side of the source/drain region being opposite the first side of the source/drain region.

Abstract: A semiconductor structure includes a first transistor device, a second transistor device, and a dielectric pillar structure disposed between the first transistor device and the second transistor device. The dielectric pillar structure includes a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device.

Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

Abstract: A semiconductor structure including a stacked transistor structure comprising a top device stacked directly above a bottom device, and a bilayer gate dielectric layer separating the top device from the bottom device.

Abstract: A method of forming interconnects is provided. The method includes forming a plurality of mandrels on an interlayer dielectric (ILD) layer. The method further includes forming sidewall spacers on opposite sides of the each mandrel, wherein a portion of the ILD layer is exposed between adjacent sidewall spacers on adjacent mandrels, and removing the exposed portions of the ILD layer to form a first set of trenches between adjacent sidewall spacers. The method further includes forming a first set of interconnects in the first set of trenches, and removing the mandrels to expose portions of the ILD layer between the sidewall spacers. The method further includes removing the exposed portions of the ILD layer to form a second set of trenches between the sidewall spacers, and forming a second set of interconnects in the second set of trenches.

Abstract: A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

Abstract: A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Abstract: A contact structure having reduced middle-of-the-line (MOL) resistance is provided that includes a source/drain contact which includes a liner and a via contact that is liner-less. The via contact includes a first via portion having a first critical dimension and a second via portion having a second critical dimension that is greater than the first critical dimension. The second critical dimension provides a maximized via contact bottom critical dimension over the source/drain contact, while the first critical dimension provides sufficient area between the first via portion of the via contact and a neighboring electrically conductive structure thus avoiding any shorts between those two elements.

Abstract: Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.

Abstract: A semiconductor structure is provided that includes a pFET located in a pFET device region, the pFET includes a first functional gate structure and a plurality of pFET semiconductor channel material nanosheets, and an nFET located in the nFET device region, the nFET includes a second functional gate structure and a plurality of pFET semiconductor channel material nanosheets. The pFET semiconductor channel material nanosheets can be staggered relative to, or vertically aligned in a horizontal direction with, the nFET semiconductor channel material nanosheets. When staggered, a bottom dielectric isolation structure can be located in both the device regions, and the second functional gate structures has a bottommost surface that extends beneath a topmost surface of the bottom dielectric isolation structure. When horizontally aligned, a vertical dielectric pillar is located between the two device regions.

Abstract: A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Abstract: A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

Abstract: A semiconductor structure includes a capacitor structure at least partially disposed in a trench of an interlayer dielectric layer. The capacitor structure includes first and second electrode layers separated by a dielectric layer. A top surface of the first electrode layer is below a top surface of the second electrode layer and the dielectric layer. A spacer is disposed on the first electrode layer and a contact is disposed in the trench and connected to the second electrode layer and the spacer.

Abstract: An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.

Abstract: Embodiments of the present invention are directed to stacked field effect transistors (SFETs) having integrated vertical inverters. In a non-limiting embodiment, a first nanosheet is vertically stacked over a second nanosheet. A common gate is formed around a channel region of the first and second nanosheets. A top source or drain region is formed in direct contact with the first nanosheet and a bottom source or drain region is formed in direct contact with the second nanosheet. A first portion of the top source or drain region is shorted to a first portion of the bottom source or drain region to define a common source or drain region. A second portion of the top source or drain region is electrically coupled to a second portion of the bottom source or drain region in series through the first nanosheet, the common source or drain region, and the second nanosheet.

Abstract: A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.