Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor, a second transistor, and a third transistor separated by their respective source/drain regions; and a diffusion break between the second transistor and the third transistor, wherein a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor is more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure that includes a channel region comprising vertically stacked channels of at least two III-V semiconductor material layers having a two dimensional electron gas regions at an interface of the at least two III-V semiconductor material layers; a gate all around (GAA) geometry gate structure present on the channel region; and source and drain regions on opposing sides of the channel region.

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

Abstract: Interconnect structures including parallel metal lines and cut regions in selected ones of the parallel metal lines are fabricated without damage, even at a very small metal pitch. A dielectric fill in the cut regions has a smaller width than the width of the metal lines. Metal line width can be increased by selective metal deposition on sidewalls of the metal lines subsequent to forming the cut regions.

Abstract: A semiconductor structure includes a substrate and a field effect transistor disposed on the substrate. The field effect transistor includes a vertical fin, source and drain regions separated by a gate region, a gate structure disposed over the gate region and a gate airgap spacer at least partially disposed about the gate structure.

Abstract: A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.

Abstract: An approach provides a semiconductor structure with one or more rectangular or square-shaped contact vias in a semiconductor material. The semiconductor device includes one of the first element of the semiconductor device element under the square-shaped contact via or the second element of the semiconductor device element above the square-shaped contact via. The semiconductor structure includes the square-shaped via in the semiconductor material that has straight edges that are parallel to one or more of the (110) crystal planes of the semiconductor material and the square-shaped contact vias has corners pointing in a direction orthogonal to one or more of the (100) crystal planes of the semiconductor material. The square-shaped contact via provides a larger contact area that a conventional round-shaped contact via with a diameter matching the width of the square-shaped contact via.

Abstract: Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

Abstract: A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.

Abstract: A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.

Abstract: A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.

Abstract: Embodiments of present invention provide a method of forming electrode to a magnetic-tunnel junction device. The method includes providing a supporting structure; depositing a layer of conductive material on top of the supporting structure; performing a first etching of the layer of conductive material to form a connection layer; and performing a second etching of a remaining portion of the layer of conductive material to form a micro-stud, the micro-stud being directly above the connection layer. In one embodiment the supporting structure includes a via opening and the conductive material fills the via opening to form a via.

Abstract: Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.

Abstract: A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.

Abstract: A cross-couple contact structure is provided that is located on, and physically contacts, a topmost surface of a functional gate structure that is located laterally adjacent to a gate cut region. The cross-couple contact structure extends into the laterally adjacent gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of a first sidewall of a dielectric plug that is present in the gate cut region, and an upper surface of a dielectric liner that is located on a lower portion of the first sidewall of the dielectric plug.

Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

Abstract: A system includes an emitter unit that generates random numbers encoded in light polarization, and a detector unit positioned with respect to the emitter. The detector receives the random numbers from the emitter and converts them into an electrical signal.

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and a dielectric nanosheet as a top layer of the nanosheet stack is provided above a semiconductor substrate. A dummy gate with a gate cap and spacers on the sidewalls straddle over the nanosheet stack. End portions of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer material layer is formed. A source/drain region is formed on the sidewalls of each semiconductor channel material nanosheet. The dummy gate and gate cap are removed. Each sacrificial semiconductor material nanosheet is removed. A functional gate structure is formed that wraps around each suspended semiconductor channel material nanosheet. A self-aligned source/drain contact region is formed.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.