Abstract: A power module includes N inverter units outputting N AC voltages and being coupled to N high-frequency AC terminals, wherein the N high-frequency AC terminals are cascaded and connected to a post-stage rectifier circuit. A phase-shift control method for the power module includes: setting at least two phase-shift sequences, wherein phase sequence numbers of the N AC voltages of the N inverter units are different in the at least two phase-shift sequences; in one switching period, controlling the N AC voltages of the N inverter units to shift a first angle according to a first phase-shift sequence of the at least two phase-shift sequences; and in another switching period, controlling the N AC voltages of the N inverter units to shift the first angle according to a second phase-shift sequence of the at least two phase-shift sequences.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: An electronic device includes a substrate, a driving element, a first transparent conductive layer, an insulating layer, and a second transparent conductive layer. The driving element is disposed on the substrate and includes a drain electrode having a first edge. The first transparent conductive layer is disposed on the driving element. The insulating layer is disposed between the driving element and the first transparent conductive layer and includes a hole through which the first transparent conductive layer is electrically connected to the driving element. The second transparent conductive layer is disposed on the insulating layer. One of the first and second transparent conductive layers includes at least one slit, and the first or second transparent conductive layer that includes the at least one slit has a second edge. The second edge is located in the hole, and the at least one slit exposes the first edge of the drain electrode.

Abstract: The application provides a dispersed carrier phase-shifting method and system. The method includes connecting at least two power modules to form a modular system; each power module including a control module for sampling at least twice a common state variate, signs of slopes of the common state variate at a first and second sampling time are opposite, and a reference time of the first sampling time for each control module is the same; and regulating a carrier frequency of the power module according to a relative size between a sampled values at the first and second sampling time. According to embodiments herein, carrier phase-shifting of modular system may be implemented without communication between respective modules. Under closed-loop control, optimal carrier phase-shifting can be automatically achieved under various duty ratios, thereby having good stability.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: Embodiments relate to compositions and methods for treating solid tumors. For example, the compositions comprise modified cells comprising an isolated polynucleotide comprising a polynucleotide encoding a nuclear factor of activated T cells (NFAT) promoter operatively associated with a polynucleotide encoding FLT3L.

Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

Abstract: An electronic device has a plurality of sub-pixels. The electronic device includes a substrate, a gate line and a spacer. The gate line is disposed on the substrate and extends along a first direction. The spacer is disposed on the gate line and overlaps with the gate line. The spacer has a first width W1 along the first direction. One of the plurality of sub-pixels has a sub-pixel pitch P along the first direction. The first width W1 and the sub-pixel pitch P satisfy the following relationship: P?W1.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: Systems and techniques disclosed in this patent document provide novel and efficient ground transportation of goods by self-driving trucks based on a system of infrastructures with shipping hub facilities serving as warehouses and services centers in accordance with unique characteristics of operating autonomous self-driving trucks without entirely relying on human drivers, including features to cover technological issues, fleet management issues, and customer service issues. In addition, the disclosed systems and techniques may be implemented to integrate other fleet services and modes of transportation of goods with transportation services by self-driving trucks.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.

Abstract: A display device includes a first pixel region and a second pixel region adjacent to the first pixel region. The display device includes: a first substrate; a second substrate opposite to the first substrate; and a plurality of spacers disposed between the first substrate and the second substrate. Herein, a first portion of the plurality of spacers are disposed in the first pixel region, a second portion of the plurality of spacers are disposed in the second pixel region, a disposition density of the second portion of the plurality of spacers in the second pixel region is different from a disposition density of the first portion of the plurality of spacers in the first pixel region.

Abstract: A system for three-dimensional geometric guided student-teacher feature matching includes a multi-modal teacher model configured to determine feature matching between a pair of RGB-D images, each RGB-D image being a combination of a RGB image and its corresponding depth image; a mono-modal student model configured to determine feature matching from the pair of RGB images and the teacher model, the teacher model guiding the student model to learn RGB-induced depth information for the feature matching on both coarse and fine levels; a coarse-level knowledge transfer loss function for determining loss of transferring coarse-level matching knowledge from the teacher model to the student model; and a fine-level knowledge transfer loss function for determining loss of transferring fine-level matching knowledge from the teacher model to the student model, wherein the fine-level knowledge transfer loss function guides the student model to learn a fine-level prediction distribution with priority.

Abstract: The present invention relates to variant Cas12i4 polypeptides, methods of producing the variant Cas12i4 polypeptides, processes for characterizing the variant Cas12i4 polypeptides, cells comprising the variant Cas12i4 polypeptides, and methods of using the variant Cas12i4 polypeptides. The invention further relates to complexes comprising a variant Cas12i4 polypeptide and an RNA guide, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: A method and a system for processing a data flow with an incomplete comparison process are provided. The method is implemented by a network device that includes a flow table and a flow filter in a memory thereof. A flow analyzing module is provided for analyzing and classifying packets of an input flow, and identifying an application category to which the input flow belongs. The flow table is queried according to a result of resolving the input flow for determining whether the input flow matches any flow entry of the flow table. The flow filter is queried if the input flow fails to match any flow entry of the flow table for determining whether features of the input flow match conditions of the flow filter. The input flow is processed accordingly, without needing to copy all flows that do not match the flow entries to the flow table.

Abstract: A physiological signal sensing system and a physiological signal sensing method are provided. The physiological signal sensing system includes a signal processing device and a physiological signal sensing device having a plurality of sensing electrodes. The sensing electrodes are used to contact the skin of an organism to sense a plurality of physiological signals. The signal processing device is coupled to the physiological signal sensing device to receive the physiological signals, compares these physiological signals with the reference physiological signal pattern to obtain a comparison result, selects a selected electrode pair from the sensing electrodes based on the comparison result, and uses the selected electrode pair to perform physiological signal measurement on the organism during a normal operation period.

Abstract: The present invention relates to variant polypeptides, methods of preparing the variant polypeptides, processes for characterizing the variant polypeptides, compositions and cells comprising the variant polypeptides, and methods of using the variant polypeptides. The invention further relates to complexes comprising the variant polypeptides, methods of producing the complexes, processes for characterizing the complexes, cells comprising the complexes, and methods of using the complexes.

Abstract: A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.