Abstract: Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The method for manufacturing a backside illuminated image sensor device structure includes providing a substrate and forming a polysilicon layer over the substrate. The method further includes forming a buffer layer over the polysilicon layer and forming an etch stop layer over the buffer layer. The method further includes forming a hard mask layer over the etch stop layer and patterning the hard mask layer to form an opening in the hard mask layer. The method further includes performing an implant process through the opening of the hard mask layer to form a doped region in the substrate and removing the hard mask layer by a first removing process. The method further includes removing the etch stop layer by a second removing process and removing the buffer layer by a third removing process.

Abstract: A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.

Abstract: Embodiments of the invention provide several antenna designs that exhibit both high bandwidth and efficiency, such as for operation in one or more bands, such as but not limited to operation in 3G, 4G, LTE bands. A first aspect of the invention concerns the form factor of the enhanced antenna; a second aspect of the invention concerns the ease with which the enhanced antenna is manufactured; and a third aspect concerns the superior performance exhibited by the enhanced antenna across one or more bandwidths.

Abstract: An antenna structure comprising a dielectric substrate layer and a patch layer laminated on top of the dielectric substrate layer, wherein the antenna structure is adapted to provide dual band coverage by combining a patch mode and a slot mode configuration.

Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.

Abstract: One or more techniques or systems for mitigating peeling associated with a pad, such as a pad of a semiconductor, are provided herein. In some embodiments, a pad structure for mitigating peeling comprises a bond region located above a first region. In some embodiments, a first inter-layer dielectric region associated with the first region is formed in an inter-layer region under the pad. Additionally, a first inter-metal dielectric region associated with the first region is formed in an inter-metal region under the inter-layer region. In some embodiments, the first inter-metal region is formed under the first inter-layer region. In this manner, peeling associated with the pad structure is mitigated, at least because the first inter-metal dielectric region comprises dielectric material and the first inter-layer dielectric region comprises dielectric material, thus forming a dielectric-dielectric interface between the first inter-metal dielectric region and the inter-layer dielectric region.

Abstract: Antenna designs are disclosed that exhibit both high bandwidth and efficiency. A first aspect of the invention concerns the form factor of the antenna; a second aspect of the invention concerns the ease with which the antenna is manufactured; and a third aspect concerns the superior performance exhibits by the antenna across a large bandwidth.

Abstract: An improved structure of cooling tower includes a fan housing with a fan disposed therein, induction openings distributed on the fan housing and located below the fan, and a diffuser stack disposed at one end surface of the fan housing. In operation, cold air is drawn into the cooling tower by the fan through inlet openings of the cooling tower so as to exchange heat with the condensing water within a water chiller. When warm and wet air is drawn out of the cooling tower and the warm and wet air outside the cooling tower is induced in through the induction openings and then is drawn out, circulation reflux of warm and wet air, which tends to occur in conventional cooling towers, can be avoided and therefore increase the efficiency of the water chiller.

Abstract: An improved structure of cooling tower includes a fan housing with a fan disposed therein, induction openings distributed on the fan housing and located below the fan, and a diffuser stack disposed at one end surface of the fan housing. In operation, cold air is drawn into the cooling tower by the fan through inlet openings of the cooling tower so as to exchange heat with the condensing water within a water chiller. When warm and wet air is drawn out of the cooling tower and the warm and wet air outside the cooling tower is induced in through the induction openings and then is drawn out, circulation reflux of warm and wet air, which tends to occur in conventional cooling towers, can be avoided and therefore increase the efficiency of the water chiller.

Abstract: The configurations of a distributed power architecture are provided. The proposed distributed power architecture includes a first converter having a first power stage, a plurality of second converter, each of which has a second power stage and is coupled to the first converter, and a centralized control unit controlling the first converter and the plurality of second converters.

Abstract: A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

Abstract: An anti-vibration fan includes a frame, a bottom chassis and an elastic frame. The elastic frame includes a plurality of curved plate-like suspending arms, each having a first suspending arm section. An end of the suspending arm section has a bent section with a curved shape at its middle section, and an end of the bent section has a second suspending arm section. The bottom chassis includes a disc body and a plurality of protruding ribs extended upward from the disc body and connected to the first suspending arm section. The second suspending arm section is connected to a frame body of the frame, and the plurality of suspending arms form the elastic frame. After vanes are pivotally connected to the bottom chassis, the elastic frame cancels out the vibration force produced by the rotating vanes, so as to reduce noises and enhance the life expectancy of vanes effectively.

Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

Abstract: A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

Abstract: A high-voltage transistor device with an interlayer dielectric (ILD) etch stop layer for use in a subsequent contact hole process is provided. The etch stop layer is a high-resistivity film having a resistivity greater than 10 ohm-cm, thus leakage is prevented and breakdown voltage is improved when driving a high voltage greater than 5V at the gate site. A method for fabricating the high-voltage device is compatible with current low-voltage device processes and middle-voltage device processes.

Abstract: An oscillator device including at least an inductor, a resistor, a transistor and a capacitor is disclosed. The oscillator device further includes a first transmission layer for electrically connecting the capacitor, the resistor and the transistor; a second transmission layer for forming the inductor; two ground layers electrically connected to the first and the second transmission layers and interconnected for providing a standard potential level; and three isolation layers located between the transmission layers and the ground layers for isolating the transmission layers from the ground layers.