Patents by Inventor Chia-Wei Liu

Chia-Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9871067
    Abstract: An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ying Wu, Li-Hsin Chu, Chung-Chuan Tseng, Chia-Wei Liu
  • Publication number: 20170372963
    Abstract: A method of partitioning a wafer includes defining a scribe line surrounding a set of dies. The method further includes etching a plurality of trenches into the wafer, wherein each trench of the plurality of trenches is located between adjacent dies of the set of dies, and a width of each trench of the plurality of trenches is less than a width of the scribe line. The method further includes thinning the wafer to expose a bottom surface of the plurality of trenches. The method further includes cutting along the scribe line to separate the set of dies from another portion of the wafer.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Wei-Hsiang HUANG, Chung-Chuan TSENG, Chia-Wei LIU, Li Hsin CHU
  • Publication number: 20170263694
    Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Fang-Ting KUO, Ren-Wei XIAO, Sheng Yu LIN, Chia-Wei LIU, Chun Hua CHANG, Chien-Ying WU
  • Publication number: 20170237174
    Abstract: A broad band diversity antenna system comprises a system of log periodic antennas (LPA) and dipole antennas. Two LPAs form a balanced dipole by feeding the back ends of the LPA. The feed is improved by the addition of a balun to ensure RF balance. Because a dipole only requires narrow bandwidth, a simple balun is constructed from coax cable or a transmission line, thus providing low cost construction.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 17, 2017
    Inventors: Paul NYSEN, Chia-Wei LIU
  • Publication number: 20170237172
    Abstract: A dual band end fed dipole provides at least two distinct operating frequencies, e.g. 2.45 GHz and 5.5 GHz. Properties of the antenna include low cost to manufacture, e.g. ease of automation; minimal manual labor to manufacture, e.g. reliability; dual band operation; broad bandwidth; good feed line isolation; omnidirectional beam pattern; minimal vertical beam squint; small diameter; and high efficiency. Embodiments of the invention provide a dual band end fed dipole with a low band trap on the feed side that requires minimal manual labor to manufacture because the antenna is formed from a single flat sheet of metal and soldering is replaced with crimping. Minimal dielectric loading is also achieved.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 17, 2017
    Inventors: Paul NYSEN, Chia-Wei LIU
  • Publication number: 20170207113
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hsiang TSAI, Chung-Chuan TSENG, Chia-Wei LIU, Li-Hsin CHU
  • Patent number: 9699897
    Abstract: One or more techniques or systems for mitigating peeling associated with a pad, such as a pad of a semiconductor, are provided herein. In some embodiments, a pad structure for mitigating peeling comprises a bond region located above a first region. In some embodiments, a first inter-layer dielectric region associated with the first region is formed in an inter-layer region under the pad. Additionally, a first inter-metal dielectric region associated with the first region is formed in an inter-metal region under the inter-layer region. In some embodiments, the first inter-metal region is formed under the first inter-layer region. In this manner, peeling associated with the pad structure is mitigated, at least because the first inter-metal dielectric region comprises dielectric material and the first inter-layer dielectric region comprises dielectric material, thus forming a dielectric-dielectric interface between the first inter-metal dielectric region and the inter-layer dielectric region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Szu-Ying Chen, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chia-Wei Liu, Chung-Chuan Tseng
  • Patent number: 9691807
    Abstract: A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiao-Chi Wang, Chung-Chuan Tseng, Li-Hsin Chu, Chia-Wei Liu
  • Publication number: 20170179030
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 22, 2017
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Fang-Ting Kuo, Ren-Wei Xiao
  • Patent number: 9666660
    Abstract: A metal insulator metal (MIM) capacitor includes a base layer and a copper bulk layer in the base layer. The MIM capacitor further includes an etch stop layer over the base layer and the copper bulk layer and an oxide-based dielectric layer over the etch stop layer. The MIM capacitor further includes a capacitor bottom layer over the oxide-based dielectric layer, an insulator layer over the capacitor bottom layer, and a capacitor top layer over the insulator layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fang-Ting Kuo, Ren-Wei Xiao, Sheng Yu Lin, Chia-Wei Liu, Chun Hua Chang, Chien-Ying Wu
  • Publication number: 20170141148
    Abstract: An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor.
    Type: Application
    Filed: February 23, 2016
    Publication date: May 18, 2017
    Inventors: Chien-Ying WU, Li-Hsin CHU, Chung-Chuan TSENG, Chia-Wei LIU
  • Patent number: 9627249
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Chia-Wei Liu, Li-Hsin Chu
  • Patent number: 9627767
    Abstract: Antenna designs are disclosed that exhibit both high bandwidth and efficiency. A first aspect of the invention concerns the form factor of the antenna; a second aspect of the invention concerns the ease with which the antenna is manufactured; and a third aspect concerns the superior performance exhibits by the antenna across a large bandwidth.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 18, 2017
    Assignee: NETGEAR, INC.
    Inventors: Chia-Wei Liu, Joseph Amalan Arul Emmanuel
  • Patent number: 9620551
    Abstract: A backside illuminated image sensor device structure and methods for forming the same are provided. The method for manufacturing a backside illuminated image sensor device structure includes providing a substrate and forming a polysilicon layer over the substrate. The method further includes forming a buffer layer over the polysilicon layer and forming an etch stop layer over the buffer layer. The method further includes forming a hard mask layer over the etch stop layer and patterning the hard mask layer to form an opening in the hard mask layer. The method further includes performing an implant process through the opening of the hard mask layer to form a doped region in the substrate and removing the hard mask layer by a first removing process. The method further includes removing the etch stop layer by a second removing process and removing the buffer layer by a third removing process.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Li-Hsin Chu, Yu-Hsiang Tsai
  • Publication number: 20170085278
    Abstract: Systems and methods for enabling a WLAN client to communicate simultaneously over more than one band at a time are described, where each client has at least one radio that is operational in each supported band. Load balancing based on traffic requirements optimizes the use of the multiple bands.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Joseph Amalan Arul Emmanuel, Peiman Amini, Chia-Wei Liu
  • Publication number: 20170084479
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Yu-Hsiang TSAI, Chung-Chuan TSENG, Chia-Wei LIU, Li-Hsin CHU
  • Patent number: 9590661
    Abstract: Various embodiments disclose systems and methods for employing a Sub1G signal (e.g. a signal in the range of approximately 500 Mhz or 800 mHz) for use with internal and/or external components of various user devices. The Sub1G region may provide a path loss advantage over traditional 2.4 and 5 Ghz systems because of the lower frequency in free-space path loss model. Sub 1G may also present less interference compared to 2.4 GHz (e.g., better QoS for applications such as VOIP, Gaming, etc.). In some of the disclosed embodiments, Sub1G may be employed using current 2.4G or 5G Wireless LAN chipset with RF Up/Down Converters. In some embodiments, the Sub1G approach may be used to create a Long Range Bridge, Long Range Extender, Long Range Client, Long Range Hotspot, etc.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: March 7, 2017
    Assignee: Netgear, Inc.
    Inventors: Joseph Amalan Arul Emmanuel, Peiman Amini, Paul Nysen, Shun-Liang Yu, Chia-Wei Liu, Shahrokh Zardoshti, Gin Wang, Henry Chen
  • Publication number: 20170041028
    Abstract: Various embodiments disclose systems and methods for employing a Sub1G signal (e.g. a signal in the range of approximately 500 Mhz or 800 mHz) for use with internal and/or external components of various user devices. The Sub1G region may provide a path loss advantage over traditional 2.4 and 5 Ghz systems because of the lower frequency in free-space path loss model. Sub1G may also present less interference compared to 2.4 GHz (e.g., better QoS for applications such as VOIP, Gaining, etc.). In some of the disclosed embodiments, Sub1G may be employed using current 2.4G or 5G Wireless LAN chipset with RF Up/Down Converters. In some embodiments, the Sub1G approach may be used to create a Long Range Bridge, Long Range Extender, Long Range Client, Long Range Hotspot, etc.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Joseph Amalan Arul EMMANUEL, Peiman AMINI, Paul NYSEN, Shun-Liang YU, Chia-Wei LIU, Shahrokh ZARDOSHTI, Gin WANG, Henry CHEN
  • Patent number: 9530690
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Cindy Kuo, Ren-Wei Xiao
  • Patent number: 9524997
    Abstract: A semiconductor device includes a thermal conductor formed on and thermally connected to the seal ring. The thermal conductor is spatially spaced from the electrically conductive pad. The thermal conductor is exposed of the substrate and can be regarded as an extension of the thermal path of the seal ring, such that the heat from the seal ring is dissipated efficiently.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Wei Zhuang, Chung-Chuan Tseng, Chia-Wei Liu, Li-Hsin Chu