Abstract: A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.

Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.

Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.

Abstract: A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.

Abstract: A circuit board structure includes a circuit layer structure, an electronic component, and a stopper. The circuit layer structure includes a plurality of dielectric layers and circuits in the dielectric layers. The electronic component is disposed in the circuit layer structure; the electronic component includes a chip and a conductive bump; the chip has a first surface and a second surface that are oppositely disposed, and the first surface of the chip contacts one of the dielectric layers; the conductive bump is on the second surface of the chip and is electrically connected to the chip. The stopper is within the circuit layer structure and abuts against the conductive bump. A method for fabricating a circuit board structure is also provided herein.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A chip package structure includes a circuit structure, a redistribution structure, a heat conductive component, a chip, and a heat sink. The circuit structure includes a first circuit layer. The redistribution structure is disposed on the circuit structure and includes a second circuit layer, wherein the redistribution structure has an opening. The heat conductive component is disposed on the circuit structure and covered by the redistribution structure. The heat conductive component has a horizontal portion and a vertical portion. The horizontal portion extends toward the opening until it exceeds the opening. The vertical portion extends upward beyond the top surface of the redistribution structure from a part of the horizontal portion. The chip is disposed in the opening, and the bottom of the chip contacts the heat conductive component. The heat sink is disposed over the redistribution structure and the chip.

Abstract: A heat dissipation substrate includes an inner circuit structure, a first build-up circuit structure and a heat dissipation channel. The first build-up circuit structure is disposed on the inner circuit structure, and includes an interlayer dielectric layer, a first dielectric layer, a first patterned conductive layer and a plurality of first conductive vias. The first patterned conductive layer and the first dielectric layer are sequentially stacked on the interlayer dielectric layer. The heat dissipation channel is disposed around the chip disposing area on the first build-up circuit structure and has a first opening and a second opening. The first opening penetrates through the first dielectric layer and exposes a portion of the interlayer dielectric layer. The second opening is disposed on a side surface of the first build-up circuit structure. The first opening is in communication with the second opening.

Abstract: An electronic device for checking a randomness of an identification key device, a random key checker circuit for an electronic device and a method of checking randomness for an electronic device. An electronic device for checking a randomness of an identification key device includes an identification key generator, configured to generate an identification key. A random key checker circuit, configured to receive the identification key from the identification key generator, calculates a randomness value of the identification key according to the identification key for checking a randomness of the identification key and generates an output of the identification key with high randomness.

Abstract: An electronic device includes an audio reception circuit, a processing circuit and at least one movable component. The audio reception circuit receives an audio data. The processing circuit performs an audio feature analysis on the audio data to obtain audio feature data, and determines a corresponding action event according to audio feature data to generate an action control signal corresponding to the action event. The movable component performs the action event in response to the action control signal.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.

Abstract: A circuit carrier structure includes a glass substrate, an anti-warping layer, a conductive layer, a build-up circuit layer, and a conductive via. The glass substrate has a first surface, a second surface opposite to the first surface, and a through groove penetrating the glass substrate. The anti-warping layer is disposed on the first surface of the glass substrate and has at least one first opening and a second opening. The conductive layer is disposed in the first opening of the anti-warping layer. The build-up circuit layer is disposed on the second surface of the glass substrate. The conductive via penetrates the glass substrate. The conductive via is disposed corresponding to the first opening of the anti-warping layer, and the through groove is disposed corresponding to the second opening of the anti-warping layer, and the through groove exposes a portion of the build-up circuit layer.