Abstract: A heat dissipation substrate includes an inner circuit structure, a first build-up circuit structure and a heat dissipation channel. The first build-up circuit structure is disposed on the inner circuit structure, and includes an interlayer dielectric layer, a first dielectric layer, a first patterned conductive layer and a plurality of first conductive vias. The first patterned conductive layer and the first dielectric layer are sequentially stacked on the interlayer dielectric layer. The heat dissipation channel is disposed around the chip disposing area on the first build-up circuit structure and has a first opening and a second opening. The first opening penetrates through the first dielectric layer and exposes a portion of the interlayer dielectric layer. The second opening is disposed on a side surface of the first build-up circuit structure. The first opening is in communication with the second opening.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: A substrate structure includes a first circuit structure, a second dielectric layer, and a second circuit structure. The first circuit structure includes a first layer and a second layer. The first layer includes a first dielectric layer and a first circuit layer embedded in the first dielectric layer. The second layer is disposed below the first layer and includes a second circuit layer electrically connected to the first circuit layer. The second dielectric layer is disposed on the first circuit structure and has a first opening exposing a portion of the first circuit layer. The melting point of the second dielectric layer is lower than that of the first dielectric layer. The second circuit structure is disposed on the second dielectric layer and has a second opening connected to the first opening. The second circuit structure includes a third circuit layer electrically connected to the first circuit layer.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: A voice enhancement method for distributed system is disclosed. In the method of the present invention, a plurality of picking devices are disposed in a space for picking voice signal. The picking devices communicate with each other and have an enhancement operation on the voice information from each picking device to generate an enhanced voice signal.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A physically unclonable function (PUF) generator includes a first sense amplifier that has a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The first sense amplifier is configured to compare accessing speeds of the first and second memory cells of the plurality of memory cells. Based on the comparison of the accessing speeds, the sense amplifier provides a first output signal for generating a PUF signature. A controller is configured to output an enable signal to the first sense amplifier, which has a first input terminal configured to receive a signal from a bit line of the first memory cell and a second input terminal configured to receive a signal from a bit line of the second memory cell.

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.

Abstract: Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.

Abstract: A wireless speaker system including one or more self-propelled speaker device is provided. The self-propelled speaker device includes a processing unit, a wireless audio transmitter/receiver unit, a speaker unit, a tracking unit, and an actuator. The wireless audio transmitter/receiver unit is coupled to the processing unit and configured to receive an audio signal via a wireless transmission interface. The speaker unit is coupled to the processing unit and configured to produce sound according to the audio signal. The tracking unit is coupled to the processing unit and configured to track a location of a mobile device. The actuator is coupled to the processing unit. The processing unit controls the actuator according to the location of the mobile device. The actuator drives the self-propelled speaker device to move along with the mobile device.

Abstract: A wireless speaker system including one or more self-propelled speaker device is provided. The self-propelled speaker device includes a processing unit, a wireless audio transmitter/receiver unit, a speaker unit, a tracking unit, and an actuator. The wireless audio transmitter/receiver unit is coupled to the processing unit and configured to receive an audio signal via a wireless transmission interface. The speaker unit is coupled to the processing unit and configured to produce sound according to the audio signal. The tracking unit is coupled to the processing unit and configured to track a location of a mobile device. The actuator is coupled to the processing unit. The processing unit controls the actuator according to the location of the mobile device. The actuator drives the self-propelled speaker device to move along with the mobile device.

Abstract: The present invention provides an apparatus and method for reducing harmonic interference to GPS signal reception. The apparatus comprises a RF transceiver module, a GPS signal reception path, and a harmonic distortion predictor. The RF transceiver module generates a first signal to be transmitted. The harmonic distortion predictor is used for establishing an estimated harmonic distortion sample based on the first signal. The GPS signal reception path receives an analog GPS signal, and converts the analog GPS signal into a digital GPS signal. The digital GPS signal subtracts the estimated harmonic distortion sample to obtain an accurate digital GPS signal. Thereby, the harmonic interference may be eliminated from the GPS signal in digital domain by means of digitally form so as to reduce distortion of the GPS signal.

Abstract: An electronic device includes an audio reception circuit, a processing circuit and at least one movable component. The audio reception circuit receives an audio data. The processing circuit performs an audio feature analysis on the audio data to obtain audio feature data, and determines a corresponding action event according to audio feature data to generate an action control signal corresponding to the action event. The movable component performs the action event in response to the action control signal.