Abstract: An electronic package is provided, which includes: a substrate; at least an electronic element disposed on the substrate; an antenna structure disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the electronic element and the antenna structure. Therein, the antenna structure has an extension portion and a plurality of support portions connected to the extension portion for supporting the extension portion over the substrate so as to save the surface area of the substrate, thereby meeting the miniaturization requirement of the electronic package.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

Abstract: A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract: A frequency tunable filter and an associated apparatus are provided, where the frequency tunable filter may include a plurality of ports including an input port and an output port, and may further include an inductor-capacitor (LC) resonator, a switching unit that is coupled between the LC resonator and a ground terminal of the frequency tunable filter, and a resonance adjustment unit that is coupled between the LC resonator and the ground terminal. For example, the LC resonator may include a first terminal coupled to each of the input port and the output port, and may further include a second terminal, the switching unit may selectively provide a conduction path between the second terminal of the LC resonator and the ground terminal, and the resonance adjustment unit may selectively change a resonance characteristic of the LC resonator.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller equally distributes the TLC-data blocks into three regions. In a first stage, the controller determines a first TLC-data block corresponding to the logic address of a prewrite data sector, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data. When the first TLC-data block does not have valid data, the controller selects a second TLC-data block and a third TLC-data block from the regions other than the first region for writing the prewrite data sector, into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode.

Abstract: A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract: A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

Abstract: The data storage device included a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages, and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory. The microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory and records a link table indicator on the flash memory to indicate a position of the link table. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. Further, the microcontroller erases user of logical addresses corresponding to N logical-to-physical address mapping tables.

Abstract: A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path.

Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

Abstract: The data storage device included a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages, and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory. The microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory to record mapping information between the host and the flash memory and records a link table indicator on the flash memory to indicate a position of the link table. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. Further, the microcontroller erases user of logical addresses corresponding to N logical-to-physical address mapping tables.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.