Patents by Inventor Ching-Hsiang Hsu

Ching-Hsiang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170301406
    Abstract: A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.
    Type: Application
    Filed: April 13, 2017
    Publication date: October 19, 2017
    Inventors: Wei-Zhe Wong, Ching-Hsiang Hsu, Ching-Sung Yang
  • Publication number: 20170053708
    Abstract: The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.
    Type: Application
    Filed: May 27, 2016
    Publication date: February 23, 2017
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Ching-Hsiang Hsu
  • Patent number: 9518327
    Abstract: The present invention provides a metal stripping additive, composition containing the same, and method for stripping metal by using the composition. The metal stripping additive comprises a phosphate, a carbonate, and a component selected from at least one of citric acid or a derivative thereof, oxalate or a derivative thereof, malate or a derivative thereof. The metal stripping additive is used with nitric acid as the metal stripping composition of the present invention. The present method has advantages of being capable of stripping various metals, low corrosion, low toxicity, and being applicable under ambient temperature.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 13, 2016
    Assignee: UWIN NANOTECH, CO., LTD.
    Inventor: Ching-Hsiang Hsu
  • Publication number: 20160102408
    Abstract: The present invention provides a metal stripping additive, composition containing the same, and method for stripping metal by using the composition. The metal stripping additive comprises a phosphate, a carbonate, and a component selected from at least one of citric acid or a derivative thereof, oxalate or a derivative thereof, malate or a derivative thereof. The metal stripping additive is used with nitric acid as the metal stripping composition of the present invention. The present method has advantages of being capable of stripping various metals, low corrosion, low toxicity, and being applicable under ambient temperature.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Applicant: UWin Nanotech. Co., Ltd.
    Inventor: CHING-HSIANG HSU
  • Publication number: 20150376735
    Abstract: The present invention provides an additive for tin stripping, comprising 0.1 to 20 wt % of copper corrosion inhibitor and 0.1 to 20 wt % of nickel corrosion inhibitor; wherein said weight percentage is based on the total weight of said additive. The present additive can be used with nitric acid conventionally used for metal-stripping for not only reducing the usage of nitric acid but also improving the efficiency of tin stripping. The present invention also provides a method for Tin recycle and a reaction tank for metal recycle. Both of them are favorable for satisfying the needs of metal recycle (especially, tin recycle) in the field.
    Type: Application
    Filed: May 1, 2015
    Publication date: December 31, 2015
    Applicant: UWin Nanotech. Co., Ltd.
    Inventor: CHING-HSIANG HSU
  • Patent number: 9090985
    Abstract: The invention provides a stripping gold component which could remove gold from substrate, comprising: a stripping gold chemical compound; and a assistant conductive compound wherein said stripping gold chemical compound bonds with gold to form covalent bond to strip gold from said substrate, said assistant conductive chemical compound helps the electric conduction and decreases the voltage, said substrate would not be damaged after stripping gold from said substrate, and the stripping gold component is cyanide free.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 28, 2015
    Assignee: UWIN NANOTECH CO., LTD.
    Inventor: Ching-Hsiang Hsu
  • Publication number: 20140243249
    Abstract: The present invention provides a metal stripping additive, composition containing the same, and method for stripping metal by using the composition. The metal stripping additive comprises a phosphate, a carbonate, and a component selected from at least one of citric acid or a derivative thereof, oxalate or a derivative thereof, malate or a derivative thereof. The metal stripping additive is used with nitric acid as the metal stripping composition of the present invention. The present method has advantages of being capable of stripping various metals, low corrosion, low toxicity, and being applicable under ambient temperature.
    Type: Application
    Filed: August 2, 2013
    Publication date: August 28, 2014
    Applicant: Uwin Nanotech. Co., Ltd.
    Inventor: CHING-HSIANG HSU
  • Patent number: 8646152
    Abstract: A transversely movable hinge is mounted between a base and a cover of a folding device and has a moving assembly. The moving assembly is connected to an expansion device via a linking rod. Therefore, when the folding device is opened, the expansion device is driven to extend and is convenient for users. When the folding device is closed, the expansion device is driven to retract for saving space.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: February 11, 2014
    Assignee: Shin Zu Shing Co., Ltd.
    Inventors: Zheng-Cheng Lin, Ching-Hsiang Hsu
  • Patent number: 8497172
    Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 30, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
  • Patent number: 8466519
    Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 18, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
  • Publication number: 20120292201
    Abstract: The invention provides a stripping gold component which could remove gold from substrate, comprising: a stripping gold chemical compound; and a assistant conductive compound wherein said stripping gold chemical compound bonds with gold to form covalent bond to strip gold from said substrate, said assistant conductive chemical compound helps the electric conduction and decreases the voltage, said substrate would not be damaged after stripping gold from said substrate, and the stripping gold component is cyanide free.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 22, 2012
    Applicant: UWIN NANOTECH CO., LTD.
    Inventor: Ching-Hsiang Hsu
  • Publication number: 20120291573
    Abstract: A transversely movable hinge is mounted between a base and a cover of a folding device and has a moving assembly. The moving assembly is connected to an expansion device via a linking rod. Therefore, when the folding device is opened, the expansion device is driven to extend and is convenient for users. When the folding device is closed, the expansion device is driven to retract for saving space.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Inventors: Zheng-Cheng LIN, Ching-Hsiang Hsu
  • Publication number: 20120276700
    Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Inventors: Ching-Hsiang Hsu, Ching-Sung Yang, Shih-Jye Shen
  • Patent number: 8232961
    Abstract: A pixel driving structure of a particle display displaying three colors and a method for displaying colors thereof are provided. The pixel driving structure includes a first substrate; a first electrode layer disposed on a surface of the first substrate; a second substrate disposed opposite to the first substrate; a second electrode layer on the second substrate; a particle solution disposed between the first electrode layer and the second electrode layer and having a first color solution, a plurality of second color positive particles, and a plurality of third color negative particles; and an alternating/direct power supply connecting with the first and second electrode layers. A method for displaying color includes steps of applying an alternating voltage to display a first color; applying a first direct voltage to display a third color; and applying a second direct voltage to display a second color.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: July 31, 2012
    Assignees: Chunghwa Picture Tubes, Ltd., National Chiao Tung University
    Inventors: Shih-Kang Fan, Cheng-Pu Chiu, Ching-Hsiang Hsu, Chi-Neng Mo, Mei-Tsao Chiang
  • Publication number: 20110195258
    Abstract: A microencapsulated liquid device includes: a substrate; a droplet liquid disposed on the substrate; a protecting layer covering the droplet liquid, the protecting layer being made from an encapsulating liquid that is immiscible with the droplet liquid, that has a surface energy lower than that of the droplet liquid, and that is solidified to form the protecting layer; and a cover plate covering the protecting layer. A method for making the microencapsulated liquid device is also disclosed.
    Type: Application
    Filed: August 5, 2010
    Publication date: August 11, 2011
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Shih-Kang Fan, Cheng-Pu Chiu, Ching-Hsiang Hsu
  • Patent number: 7960792
    Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: June 14, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 7952934
    Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: May 31, 2011
    Assignee: Powerflash Technology Corporation
    Inventors: Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu
  • Publication number: 20110057243
    Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.
    Type: Application
    Filed: November 11, 2010
    Publication date: March 10, 2011
    Applicant: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
  • Patent number: 7903472
    Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: March 8, 2011
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Hai-Ming Lee, Shih-Jye Shen, Ching-Hsiang Hsu
  • Publication number: 20110051526
    Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
    Type: Application
    Filed: November 11, 2010
    Publication date: March 3, 2011
    Inventors: Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu