Abstract: A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.

Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.

Abstract: A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the conductive type silicon body layer beneath the gate.

Abstract: The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

Abstract: Field color sequential (FCS) control system applied for an FCS display device is provided. The FCS control system includes an input system, a memory and an output system. The input system, including a plurality of buffers respectively corresponding to different color channels, receives different color channel components of pixels in parallel such that components of a same color channel are stored in a same buffer. The memory, including a plurality of partitions respectively corresponding to different color channels, stores components of a same color channel to a same partition in association with triggering of rising and falling edges of a clock, respectively. The output system sequentially buffers and outputs color channel components of corresponding partitions.

Abstract: Field color sequential (FCS) imaging method and technology/apparatus based on FCS principle are provided. In an embodiment, while displaying a frame based on FCS principle, the invention includes: extracting at least a monochrome subfield value and at least a mixed subfield value from each color channel of each pixel of the frame, writing corresponding monochrome subfield value of each pixel in association with a single color channel, and writing corresponding mixed subfield value of each pixel in association with a mixed color which is mixed by at least two color channels.

Abstract: A pixel driving structure of a particle display displaying three colors and a method for displaying colors thereof are provided. The pixel driving structure includes a first substrate; a first electrode layer disposed on a surface of the first substrate; a second substrate dispoed opposite to the first substrate; a second electrode layer on the second substrate; a particle solution disposed between the first electrode layer and the second electrode layer and having a first color solution, a plurality of second color positive particles, and a plurality of third color negative particles; and an alternating/direct power supply connecting with the first and second electrode layers. A method for displaying color includes steps of applying an alternating voltage to display a first color; applying a first direct voltage to display a third color; and applying a second direct voltage to display a second color.

Abstract: A bubbleless packaging method is provided. The method is applicable to package a display element. In the method, firstly, a first substrate and a first protective layer are provided. The first protective layer is formed on the first substrate. Then, a second substrate and a second protective layer are provided. The second protective layer is formed on the second substrate. Then, a plasma treatment is performed on surfaces of the first protective layer and the second protective layer. Then, the first substrate and the second substrate are dipped into a solution after the plasma treatment. Then, the first substrate and the second substrate are laminated in the solution, wherein the first protective layer faces the second protective layer. Finally, the first substrate and the second substrate are taken out from the solution.

Abstract: A display includes a first substrate, a first electrode, a second substrate, a second electrode and a display material layer. The first electrode is disposed on the first substrate and the second electrode is disposed on the second substrate. The display material layer is disposed between the first electrode and the second electrode. The display material layer of the invented display includes a solution and a plurality of first micro beads, wherein each of the first micro beads further has a plurality of different axis lengths in different axis directions, and the axis length in at least an axis direction is different from the axis lengths in the rest axis directions so that the first micro beads present different arrangement densities in different driving frequencies under the influence of polarized self-arrangement effect.

Abstract: A display includes a first substrate, a first electrode, a second substrate, a second electrode and a display material layer. The first electrode is disposed on the first substrate and the second electrode is disposed on the second substrate. The display material layer is disposed between the first electrode and the second electrode. The display material layer of the invented display includes a solution and a plurality of first micro beads, wherein each of the first micro beads further has a plurality of different axis lengths in different axis directions, and the axis length in at least an axis direction is different from the axis lengths in the rest axis directions so that the first micro beads present different arrangement densities in different driving frequencies under the influence of polarized self-arrangement effect.

Abstract: A display medium and a display are provided. The display medium includes a thermal-sensitive solution and a number of micro particles. The micro particles are dispersed in the thermal-sensitive solution. At a first temperature, the thermal-sensitive solution is in a liquid form, such that the micro particles move freely. At a second temperature, the thermal-sensitive solution is in a colloid form, such that the micro particles are fixed. The first temperature differs from the second temperature.

Abstract: A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.

Abstract: A Lactobacillus paracasei-containing product used for inhibiting dental diseases caused by bacteria is provided, which comprises a plurality of Lactobacillus paracasei for inhibiting the growth of bacteria of dental diseases. Particularly, foods, oral hygiene products or oral treatment medicine containing the Lactobacillus paracasei when being administered or applied to a user can inhibit or reduce the number of pathogens of dental caries and periodontal diseases in oral cavity of the user, thereby achieving the efficacy of preventing dental diseases, such as dental caries and periodontal diseases.

Abstract: The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

Abstract: An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling.

Abstract: For performing saturation control of one or more selected colors of the image, respective color values of the selected color(s) are pre-defined. Meanwhile, a specified pixel is selected from the image. Then distance(s) between the color space coordinate of the specified pixel and the color space coordinate(s) of the selected color(s) is (are) calculated. The color values of the specified pixel are thus adjusted depending on comparing results of the distance(s) with corresponding threshold distance(s).

Abstract: Method and related circuit for color depth enhancement of displays is provided. In an embodiment of the invention, when emulating an interpolated color level between a first and a second color levels the display can display, a color channel component of the first color level and another color channel component of the second color level are selected for color dithering and color depth enhancement.

Abstract: In an image compensation method, formats of images are identified based on ambient color quantity information. If the image is in text format or of high contrast, over compensation is barred to avoid edge effect. A compensation coefficient is set basing on edge eigenvalue of images. The compensation value is fine tuned based on a threshold value to obtain finer compensation result.

Abstract: The present invention provides a modified Dermatophagoides pteronyssinus allergen Der p 5 protein which has ability to inhibit IgE binding when exposed against to the antigen. A method for treating allergy comprising administrating a therapeutically effective dose of the modified D. pteronyssinus allergen Der p 5 protein to a subject suffering from allergy Der p 5 is also provided.

Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.