Patents by Inventor Christopher S. Moore

Christopher S. Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040098416
    Abstract: A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.
    Type: Application
    Filed: September 29, 2003
    Publication date: May 20, 2004
    Inventors: Christopher S. Moore, Derek J. Bosch, Daniel C. Steere, J. James Tringali
  • Patent number: 6738883
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: May 18, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Patent number: 6711043
    Abstract: The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: March 23, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: David R. Friedman, J. James Tringali, Roy E. Scheuerlein, James E. Schneider, Christopher S. Moore, Daniel C. Steere
  • Patent number: 6697928
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 24, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roger W. March, Daniel T. Brown, Christopher S. Moore
  • Patent number: 6694415
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 17, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20040001348
    Abstract: A multiple-mode memory includes a three-dimensional array of word lines, bit lines and memory cells. The memory cells are arranged in multiple vertically stacked layers. In some layers the memory cells are implemented as field-programmable write-once memory cells, and in other layers the memory cells are implemented as field-programmable re-writable memory cells. In this way, both re-writability and permanent data storage are provided in an inexpensive, single-chip solution. Additional types and numbers of types of memory cells can be used.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventors: Michael A. Vyvoda, Christopher S. Moore
  • Patent number: 6658438
    Abstract: A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: December 2, 2003
    Assignee: Matrix Semiconductor, INC.
    Inventors: Christopher S. Moore, Derek J. Bosch, Daniel C. Steere, J. James Tringali
  • Patent number: 6651133
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: November 18, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Christopher S. Moore, Roger W. March, Daniel T. Brown
  • Patent number: 6647471
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: November 11, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20030120858
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 26, 2003
    Applicant: MATRIX SEMICONDUCTOR, INC.
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown, Thomas H. Lee, Mark G. Johnson
  • Publication number: 20030115535
    Abstract: The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventors: Roger W. March, Christopher S. Moore, Mark G. Johnson
  • Publication number: 20030028734
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: February 6, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20030028717
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: February 6, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Patent number: 6515904
    Abstract: The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 4, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Christopher S. Moore, Bendik Kleveland, Roger W. March, James M. Cleeves, Roy E. Scheuerlein
  • Publication number: 20030023820
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 30, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20030023828
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 30, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20030023821
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 30, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown
  • Publication number: 20030018871
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 23, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown, Thomas H. Lee, Mark G. Johnson
  • Publication number: 20020167829
    Abstract: The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Application
    Filed: June 27, 2002
    Publication date: November 14, 2002
    Inventors: David R. Friedman, J. James Tringali, Roy E. Scheuerlein, James E. Schneider, Christopher S. Moore, Daniel C. Steere
  • Publication number: 20020163834
    Abstract: The preferred embodiments described herein relate to a monolithic integrated circuit comprising a three-dimensional memory array having a plurality of layers of memory cells stacked vertically above one another and above the substrate of the integrated circuit. Support circuitry for the three-dimensional memory array is formed in the substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array.
    Type: Application
    Filed: June 27, 2002
    Publication date: November 7, 2002
    Inventors: Roy E. Scheuerlein, J. James Tringali, Colm P. Lysaght, Alper Ilkbahar, Christopher S. Moore, David R. Friedman