Patents by Inventor Christopher S. Moore

Christopher S. Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020136059
    Abstract: The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Application
    Filed: June 29, 2001
    Publication date: September 26, 2002
    Inventors: Christopher S. Moore, Bendik Kleveland, Roger W. March, James M. Cleeves, Roy E. Scheuerlein
  • Publication number: 20020107862
    Abstract: The preferred embodiments described herein provide a memory device and method for reading data stored in a portion of a memory device unreadable by a file system of a host device. In one preferred embodiment, a memory device is provided comprising a first portion that is readable by a file system of a host device and a second portion that is unreadable by the file system of the host device. The first portion stores program code operative to enable the host device to read the second portion. In operation, after the memory device is connected with the host device, the program code is provided to the host device, and the host device reads the data stored in the second portion of the memory device. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 8, 2002
    Inventors: Christopher S. Moore, Roger W. March, Daniel T. Brown
  • Publication number: 20020108054
    Abstract: The preferred embodiments described herein provide a solid-state memory device storing program code and methods for use therewith. In one preferred embodiment, a solid-state memory device storing program code is provided that enables a host device to read data from or store data to the solid-state memory device. In another preferred embodiment, a solid-state memory device storing an identifier and encrypted program code is provided. When the solid-state memory device is connected to a host device, the host device decrypts the encrypted program code using the identifier. In another preferred embodiment, program code stored in a solid-state memory device is provided to a host device, and the program code allows the host device to store data only in the solid-state memory device. In another preferred embodiment, a method for distributing program code is provided.
    Type: Application
    Filed: February 2, 2001
    Publication date: August 8, 2002
    Inventors: Christopher S. Moore, Roger W. March, Daniel T. Brown
  • Patent number: 6424581
    Abstract: A write-once memory device includes a memory array controller and an electronically resetable flag. The memory array controller prevents writing and erasing from a write-once memory array unless the flag is in a selected state. The memory device is used with a data storage system that automatically determines whether a memory device installed in the data storage system is a write-once memory, and then automatically sends a recognition signal to the memory device once it has been determined to be a write-once memory. The memory device (1) automatically sets the flag in response to the recognition signal, (2) automatically refuses to implement write and erase commands prior to receipt of the recognition signal and setting of the flag, and (3) implements write and erase commands subsequent to receipt of the recognition signal and setting of the flag. The memory device implements nondestructive commands such as read and status commands regardless of the state of the flag.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: July 23, 2002
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Derek J. Bosch, Christopher S. Moore, Daniel C. Steere, J. James Tringali
  • Patent number: 6137709
    Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: October 24, 2000
    Assignee: Intel Corporation
    Inventors: Ted L. Boaz, Christopher S. Moore, Raviprakash Nagaraj
  • Patent number: 6061263
    Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventors: Ted L. Boaz, Christopher S. Moore, Raviprakash Nagaraj