Abstract: A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage levels during a normal mode of operation. Power control circuitry is coupled to a source terminal of the first p-channel transistor of each memory cell for providing to the first p-channel transistors the first reference voltage level during the normal mode of operation. This causes a first voltage less than the first reference voltage level to appear at the source terminal of the first p-channel transistors during a data corruption mode of operation wherein data stored in the one or more memory cells is corrupted.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

Abstract: A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell. The redundancy circuit may further include a plurality of redundant storage circuits for selectively maintaining data values, and redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.

Abstract: A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell. The redundancy circuit may further include a plurality of redundant storage circuits for selectively maintaining data values, and redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.

Abstract: A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A memory device having a first and a second memory section, the first and the second memory sections being coupled to bit lines. The second memory section may include at least one fuse. The first memory section includes a volatile memory and the second memory section includes a non-volatile memory. The volatile memory may be static or dynamic random access memory. The memory device may further include a control circuit connected to the at least one fuse to provide for prelaser testing.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an electrical signal, such as an unregulated power supply. The circuit includes a comparator that compares the electrical to the voltage reference and generates an output having a value that is based upon the comparison. A oscillation suppression circuit receives the output of the comparator and generates an output signal that follows the output of the comparator once the output of the comparator remains stable and in the same logic state for a predetermined of time.

Abstract: A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference voltage, the enable control circuit drives the enable input to place the CAM into a low current, stand-by mode of operation. A voltage supply back-up circuit is connected to the voltage power supply input, and operates to compare the external voltage to a supply reference voltage. If the external voltage drops below the supply reference voltage, the voltage supply back-up circuit switches the voltage power supply input for the CAM from the external voltage input to a battery backup. As an alternative, the voltage power supply input for the CAM includes a separate power input for a CAM array, and the switch causes only that separate power input for the CAM array to be powered from the battery back-up.

Abstract: A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference voltage, the enable control circuit drives the enable input to place the CAM into a low current, stand-by mode of operation. A voltage supply back-up circuit is connected to the voltage power supply input, and operates to compare the external voltage to a supply reference voltage. If the external voltage drops below the supply reference voltage, the voltage supply back-up circuit switches the voltage power supply input for the CAM from the external voltage input to a battery back-up. As an alternative, the voltage power supply input for the CAM includes a separate power input for a CAM array, and the switch causes only that separate power input for the CAM array to be powered from the battery back-up.

Abstract: A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.