Abstract: A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the level of the input signal. The enable signal may be the sense-amplifier enable signal. The signal driver may also include an input circuit that receives the input signal and generates an intermediate signal from the input signal when the enable signal has the first state. An output circuit is coupled to the input circuit, receives the intermediate signal, and generates the output signal from the intermediate signal. A switch circuit is coupled to the input circuit, receives the enable signal, and cuts off substantially all supply current to the input circuit when the enable signal has the second state.

Abstract: A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simulation circuit includes a memory cell replicate which replicates the time required for writing data to memory cells of the array. After the memory cell replicate has changed state, a signal is output via a switching circuit to the variable timer circuit for generation of a write termination signal. The memory cells are tested at various write cycle speeds by controlling the variable timer circuit. The variable timer circuit is set to terminate the write as quickly as possible after a successful write to the memory cells has been completed.

Abstract: A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

Abstract: A memory-row selector includes an address input terminal, a mode terminal, and even-row-select and odd-row-select terminals. While a test signal level occupies the mode terminal (ie., during a test mode), the selector places either an active level or an inactive level on both of the even-row-select and odd-row-select terminals. An active level on both of the select terminals enables both even-row and odd-row word lines, and allows writing to or reading from memory cells in both odd and even rows. An inactive level on both of the select terminals disables both even-row and odd-row word lines, including the word line coupled to the addressed memory cell.

Abstract: A data input circuit is used in a memory device having an externally accessible data pin. The data input circuit includes first and second data output terminals and a test terminal that receives a test signal. A data converter is coupled to the first and second data output terminals and to the test terminal, and places complementary signal levels on the first and second data output terminals when the test signal is absent from the test terminal, and places a same signal level on both the first and second data output terminals when the test signal is present on the test terminal. The data input circuit may include an input terminal that is coupled to the data pin, where the data converter is coupled to the input terminal.

Abstract: A memory device includes an array of matrix memory cells that each correspond to a matrix location within the matrix array, an array of redundant memory cells that each correspond to a redundant location within the redundant array, and address and test circuitry. During a first test mode that is performed before any redundant cells have been mapped to the addresses of matrix locations, the address and test circuitry simultaneously addresses all of the matrix locations and selects all of the redundant memory cells. During a second test mode that is performed after the first test mode, the address and test circuitry simultaneously addresses all of the matrix locations and selects only those redundant memory cells that are mapped to the addresses of matrix locations. Typically, the redundant memory cells are so mapped to replace defective matrix memory cells.

Abstract: A memory device with a sense amplifier enable line having the same resistance and capacitance as a local wordline. The sense amplifier enable line is made out of the same material, has the same layout, and has the same load placed on as a local wordline, this will make the sense amplifier enable line have the same resistance, capacitance, and load characteristics as a local wordline. The load on the sense amplifier enable line is a combination of the sense amplifier enable line operational circuitry and sense amplifier enable line load circuit.

Abstract: A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the memory cell replicate is changed upon the write sensing circuit sensing the start of a write. The memory cell replicate is preferably constructed using the same structure, design, and process as the memory cells of the array so as to accurately simulate the time required for writing data to a memory cell in the array. Upon the write to the memory cell replicate being completed, a write termination signal is generated for terminating the write signal. The write termination signal also is a reset signal for resetting circuits of the array to prepare for the next cycle, whether it be a read or a write.

Abstract: An integrated circuit is formed on a die that is formed as a detachable part of a semiconductor wafer. The wafer includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. The integrated circuit includes functional circuitry that supports normal and wafer-test modes of operation and that is coupled to the wafer test-mode path before the die is detached from the wafer. The functional circuitry is operable to function in the wafer test mode of operation when the wafer test-mode signal has a first state. The integrated circuit also includes a wafer test-mode power circuit that is coupled to the functional circuitry, and that is coupled to the wafer power-supply path and the wafer test-mode path before the die is detached from the wafer. The power circuit is operable to couple the wafer power-supply path to the functional circuitry when the wafer test-mode signal has the first state.

Abstract: A circuit and method for determining the exact time at which data begins to be written to a memory cell. A write sensing circuit is connected to a data input line. When data is presented on the data input line for writing to the memory cell, the write sensing circuit outputs a write start signal indicating that data is being presented to memory cells for writing. The actual start time of a write to a memory cell is therefore accurately timed based on the start of the write to the memory cell itself. This provides the advantage that the change in state of the data is directly sensed as the factor for measuring the start time of a write to a memory cell. The data can be sensed either directly from the bit lines or, alternatively, from a write data bus.

Abstract: The present invention is directed to a method and apparatus for testing integrated circuits using a tester with a frequency limitation lower than what is needed to fully test the integrated circuit. Clock signals, each lower than that needed to test an integrated circuit at speed, are generated by a tester. These clock signals are connected to separate output pins of the integrated circuit. At least two of the input signals are out of phase with each other. The input clock signals are combined to create a test clock signal with a higher frequency, thus allowing the integrated circuit to be tested at its normal, operating frequency. A toggle signal may be provided to an additional pin on the integrated circuit. Use of the toggle signal allows test data to be written at the maximum frequency of the integrated circuit. The present invention does not create any significant delay during normal operation of the integrated circuit, and also does not create any significant layout penalty.

Abstract: A memory device with a sense amplifier enable line having the same resistance and capacitance as a local wordline. The sense amplifier enable line is made out of the same material, has the same layout, and has the same load placed on as a local wordline, this will make the sense amplifier enable line have the same resistance, capacitance, and load characteristics as a local wordline. The load on the sense amplifier enable line is a combination of the sense amplifier enable line operational circuitry and sense amplifier enable line load circuit.

Abstract: A current source for generating a current that is relatively stable over variations in the power supply voltage and temperature, and over variations in process parameters is disclosed. The current source includes a bias circuit, for producing a compensating bias voltage, and a current mirror. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a first current mirror, which controls a current applied to a linear load device. The voltage across the load device determines the bias voltage, which is in turn applied to the gate of a transistor in the reference leg of a second current mirror. The bias voltage controls the current in the reference leg of the second current mirror, and an output leg mirrors the second reference current to produce a stable output current.

Abstract: An integrated circuit memory structure is disclosed where the read and write buses (true and complement) are coupled to redundant input/output select circuits through permanently programmable selection element that can disconnect the read and write busses from the redundant input/output select circuit.

Abstract: A memory access circuit is provided for isolating a matrix memory cell from and coupling a redundant memory cell to a data line when the matrix memory cell is defective. The memory access circuit includes a matrix switch that is coupled between the matrix memory cell and the data line. When the matrix memory cell is defective, a matrix-switch control circuit opens the matrix switch to isolate the defective memory cell from the data line. The memory access circuit also includes a redundant switch that is coupled between the redundant memory cell and the data line. When the defective matrix memory cell is addressed, a redundant-switch control circuit closes the redundant switch to couple the redundant memory cell to the data line in place of the defective memory cell.

Abstract: A circuit biases an associated pair of bit lines. A fuse is coupled between a biasing voltage and a node. A first load is coupled between the node and a first of the bit lines. A second load is coupled between the node and a second of the bit lines.

Abstract: An integrated circuit having a memory array comprised of a plurality of memory cells arranged in rows and columns and a logic circuitry including column decoder and read/write circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines extending from the memory array to the logic circuitry. In order to perform a complete voltage stress test of the memory array, inside the array true and complement bitlines are alternated so that every true bitline is adjacent exclusively to complement bitlines and every complement bitline is adjacent exclusively to true bitlines. According to a first embodiment of the invention, bitlines exiting from the memory array are connected directly to the logic circuitry, while according to a second embodiment, between the array and the logic circuitry, at least one pair of true and complement bitlines is twisted so that one bitline cross over the other.

Abstract: A driver circuit writes data to a memory cell during a write cycle and uncouples the write power terminals from the write terminals during a test mode. The driver circuit includes a first and second data input terminals that typically receive complementary data signals during a write cycle, a test terminal, a write-enable terminal, first and second write power terminals, and first and second write terminals that are coupled to the memory cell. The circuit respectively uncouples the first and second write terminals from the first and second write power terminals when a first signal level, which indicates the test mode, is present on the test terminal. The driver circuit may also couple the first and second write terminals to a reference voltage such as a ground voltage when the first signal level is present on the test terminal.

Abstract: Signal propagation times in circuit paths are matched to compensate for signal delays due to differences in the physical parameters, such as lengths, of the circuit paths. This is accomplished by adjusting the length of lead lines and by the addition of resistors in series with shorter lead lines in a chip or die. In a chip with an active device, such as logic, having multiple input lines, the lines are divided into long lines and short lines. All long lines are laid out so as to have the same length and to use the least amount of chip surface area. Similarly, all short lines are laid out on the chip so as to have the same length while using the least amount of chip surface area. With all the short lines having the same propagation time difference relative to all the long lines, the same resistive element is added to all the short lines to effect the same RC delay in signal propagation on the short lines so as to match the signal propagation time on the short lines with that on the long lines.

Abstract: An integrated circuit includes test circuitry and test mode enable circuitry. During power-up, an over-voltage on a package pin of the integrated circuit can initiate a test mode. The test mode enable signal may be latched into its activity state by a signal provided on a second package pin. Thereafter, the first and second package pins may be used in the normal voltage range during the test operations.